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d037e100d1
Clean all #ifdef's added to OMAP2 clock code to make it COMMON clk ready, not that CONFIG_COMMON_CLK is enabled. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: also drop CONFIG_COMMON_CLK tests around APLL recalc_rate functions] Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: remove some ifdefs in mach-omap2/io.c] Signed-off-by: Paul Walmsley <paul@pwsan.com>
143 lines
3.1 KiB
C
143 lines
3.1 KiB
C
/*
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* OMAP2xxx APLL clock control functions
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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* Gordon McNutt and RidgeRun, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "cm2xxx.h"
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#include "cm-regbits-24xx.h"
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/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
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#define EN_APLL_STOPPED 0
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#define EN_APLL_LOCKED 3
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/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
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#define APLLS_CLKIN_19_2MHZ 0
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#define APLLS_CLKIN_13MHZ 2
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#define APLLS_CLKIN_12MHZ 3
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/* Private functions */
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/**
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* omap2xxx_clk_apll_locked - is the APLL locked?
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* @hw: struct clk_hw * of the APLL to check
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*
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* If the APLL IP block referred to by @hw indicates that it's locked,
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* return true; otherwise, return false.
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*/
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static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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u32 r, apll_mask;
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apll_mask = EN_APLL_LOCKED << clk->enable_bit;
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r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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return ((r & apll_mask) == apll_mask) ? true : false;
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}
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int omap2_clk_apll96_enable(struct clk_hw *hw)
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{
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return omap2xxx_cm_apll96_enable();
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}
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int omap2_clk_apll54_enable(struct clk_hw *hw)
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{
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return omap2xxx_cm_apll54_enable();
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}
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static void _apll96_allow_idle(struct clk_hw_omap *clk)
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{
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omap2xxx_cm_set_apll96_auto_low_power_stop();
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}
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static void _apll96_deny_idle(struct clk_hw_omap *clk)
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{
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omap2xxx_cm_set_apll96_disable_autoidle();
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}
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static void _apll54_allow_idle(struct clk_hw_omap *clk)
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{
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omap2xxx_cm_set_apll54_auto_low_power_stop();
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}
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static void _apll54_deny_idle(struct clk_hw_omap *clk)
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{
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omap2xxx_cm_set_apll54_disable_autoidle();
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}
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void omap2_clk_apll96_disable(struct clk_hw *hw)
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{
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omap2xxx_cm_apll96_disable();
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}
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void omap2_clk_apll54_disable(struct clk_hw *hw)
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{
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omap2xxx_cm_apll54_disable();
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}
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unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0;
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}
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unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0;
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}
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/* Public data */
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const struct clk_hw_omap_ops clkhwops_apll54 = {
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.allow_idle = _apll54_allow_idle,
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.deny_idle = _apll54_deny_idle,
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};
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const struct clk_hw_omap_ops clkhwops_apll96 = {
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.allow_idle = _apll96_allow_idle,
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.deny_idle = _apll96_deny_idle,
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};
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/* Public functions */
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u32 omap2xxx_get_apll_clkin(void)
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{
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u32 aplls, srate = 0;
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aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
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aplls &= OMAP24XX_APLLS_CLKIN_MASK;
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aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
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if (aplls == APLLS_CLKIN_19_2MHZ)
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srate = 19200000;
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else if (aplls == APLLS_CLKIN_13MHZ)
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srate = 13000000;
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else if (aplls == APLLS_CLKIN_12MHZ)
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srate = 12000000;
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return srate;
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}
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