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https://github.com/edk2-porting/linux-next.git
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56e9406ca2
This patch updated Kconfig for langwell otg transceiver driver. Add ipc driver(INTEL_SCU_IPC) as a dependency. Driver version is updated too. Signed-off-by: Hao Wu <hao.wu@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
/*
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* Intel Langwell USB OTG transceiver driver
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* Copyright (C) 2008 - 2010, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef __LANGWELL_OTG_H
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#define __LANGWELL_OTG_H
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#include <linux/usb/intel_mid_otg.h>
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#define CI_USBCMD 0x30
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# define USBCMD_RST BIT(1)
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# define USBCMD_RS BIT(0)
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#define CI_USBSTS 0x34
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# define USBSTS_SLI BIT(8)
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# define USBSTS_URI BIT(6)
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# define USBSTS_PCI BIT(2)
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#define CI_PORTSC1 0x74
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# define PORTSC_PP BIT(12)
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# define PORTSC_LS (BIT(11) | BIT(10))
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# define PORTSC_SUSP BIT(7)
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# define PORTSC_CCS BIT(0)
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#define CI_HOSTPC1 0xb4
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# define HOSTPC1_PHCD BIT(22)
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#define CI_OTGSC 0xf4
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# define OTGSC_DPIE BIT(30)
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# define OTGSC_1MSE BIT(29)
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# define OTGSC_BSEIE BIT(28)
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# define OTGSC_BSVIE BIT(27)
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# define OTGSC_ASVIE BIT(26)
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# define OTGSC_AVVIE BIT(25)
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# define OTGSC_IDIE BIT(24)
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# define OTGSC_DPIS BIT(22)
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# define OTGSC_1MSS BIT(21)
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# define OTGSC_BSEIS BIT(20)
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# define OTGSC_BSVIS BIT(19)
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# define OTGSC_ASVIS BIT(18)
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# define OTGSC_AVVIS BIT(17)
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# define OTGSC_IDIS BIT(16)
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# define OTGSC_DPS BIT(14)
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# define OTGSC_1MST BIT(13)
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# define OTGSC_BSE BIT(12)
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# define OTGSC_BSV BIT(11)
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# define OTGSC_ASV BIT(10)
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# define OTGSC_AVV BIT(9)
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# define OTGSC_ID BIT(8)
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# define OTGSC_HABA BIT(7)
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# define OTGSC_HADP BIT(6)
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# define OTGSC_IDPU BIT(5)
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# define OTGSC_DP BIT(4)
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# define OTGSC_OT BIT(3)
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# define OTGSC_HAAR BIT(2)
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# define OTGSC_VC BIT(1)
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# define OTGSC_VD BIT(0)
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# define OTGSC_INTEN_MASK (0x7f << 24)
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# define OTGSC_INT_MASK (0x5f << 24)
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# define OTGSC_INTSTS_MASK (0x7f << 16)
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#define CI_USBMODE 0xf8
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# define USBMODE_CM (BIT(1) | BIT(0))
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# define USBMODE_IDLE 0
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# define USBMODE_DEVICE 0x2
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# define USBMODE_HOST 0x3
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#define USBCFG_ADDR 0xff10801c
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#define USBCFG_LEN 4
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# define USBCFG_VBUSVAL BIT(14)
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# define USBCFG_AVALID BIT(13)
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# define USBCFG_BVALID BIT(12)
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# define USBCFG_SESEND BIT(11)
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#define INTR_DUMMY_MASK (USBSTS_SLI | USBSTS_URI | USBSTS_PCI)
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enum langwell_otg_timer_type {
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TA_WAIT_VRISE_TMR,
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TA_WAIT_BCON_TMR,
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TA_AIDL_BDIS_TMR,
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TB_ASE0_BRST_TMR,
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TB_SE0_SRP_TMR,
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TB_SRP_INIT_TMR,
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TB_SRP_FAIL_TMR,
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TB_BUS_SUSPEND_TMR
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};
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#define TA_WAIT_VRISE 100
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#define TA_WAIT_BCON 30000
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#define TA_AIDL_BDIS 15000
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#define TB_ASE0_BRST 5000
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#define TB_SE0_SRP 2
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#define TB_SRP_INIT 100
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#define TB_SRP_FAIL 5500
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#define TB_BUS_SUSPEND 500
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struct langwell_otg_timer {
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unsigned long expires; /* Number of count increase to timeout */
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unsigned long count; /* Tick counter */
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void (*function)(unsigned long); /* Timeout function */
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unsigned long data; /* Data passed to function */
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struct list_head list;
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};
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struct langwell_otg {
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struct intel_mid_otg_xceiv iotg;
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struct device *dev;
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void __iomem *usbcfg; /* SCCBUSB config Reg */
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unsigned region;
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unsigned cfg_region;
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struct work_struct work;
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struct workqueue_struct *qwork;
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struct timer_list hsm_timer;
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spinlock_t lock;
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spinlock_t wq_lock;
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struct notifier_block iotg_notifier;
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};
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static inline
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struct langwell_otg *mid_xceiv_to_lnw(struct intel_mid_otg_xceiv *iotg)
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{
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return container_of(iotg, struct langwell_otg, iotg);
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}
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#endif /* __LANGWELL_OTG_H__ */
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