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32cfb1b16f
This is needed because applications using the sys_cacheflush system call can pass a memory range which isn't mapped yet even though the corresponding vma is valid. The patch also adds unwinding annotations for correct backtraces from the coherent_user_range() functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
279 lines
6.6 KiB
ArmAsm
279 lines
6.6 KiB
ArmAsm
/*
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* linux/arch/arm/mm/cache-v6.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv6 processor support.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/unwind.h>
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#include "proc-macros.S"
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#define HARVARD_CACHE
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#define CACHE_LINE_SIZE 32
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#define D_CACHE_LINE_SIZE 32
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#define BTB_FLUSH_SIZE 8
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#ifdef CONFIG_ARM_ERRATA_411920
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/*
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* Invalidate the entire I cache (this code is a workaround for the ARM1136
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* erratum 411920 - Invalidate Instruction Cache operation can fail. This
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* erratum is present in 1136, 1156 and 1176. It does not affect the MPCore.
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*
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* Registers:
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* r0 - set to 0
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* r1 - corrupted
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*/
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ENTRY(v6_icache_inval_all)
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mov r0, #0
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mrs r1, cpsr
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cpsid ifa @ disable interrupts
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mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
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msr cpsr_cx, r1 @ restore interrupts
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.rept 11 @ ARM Ltd recommends at least
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nop @ 11 NOPs
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.endr
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mov pc, lr
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#endif
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/*
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* v6_flush_cache_all()
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*
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* Flush the entire cache.
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*
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* It is assumed that:
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*/
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ENTRY(v6_flush_kern_cache_all)
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mov r0, #0
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#ifdef HARVARD_CACHE
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mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
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#ifndef CONFIG_ARM_ERRATA_411920
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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#else
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b v6_icache_inval_all
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#endif
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#else
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mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
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#endif
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mov pc, lr
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/*
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* v6_flush_cache_all()
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*
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* Flush all TLB entries in a particular address space
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*
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* - mm - mm_struct describing address space
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*/
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ENTRY(v6_flush_user_cache_all)
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/*FALLTHROUGH*/
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/*
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* v6_flush_cache_range(start, end, flags)
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*
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* Flush a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - flags - vm_area_struct flags describing address space
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*
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* It is assumed that:
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* - we have a VIPT cache.
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*/
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ENTRY(v6_flush_user_cache_range)
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mov pc, lr
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/*
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* v6_coherent_kern_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified
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* region. This is typically used when code has been written to
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* a memory region, and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*
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* It is assumed that:
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* - the Icache does not read data from the write buffer
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*/
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ENTRY(v6_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* v6_coherent_user_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified
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* region. This is typically used when code has been written to
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* a memory region, and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*
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* It is assumed that:
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* - the Icache does not read data from the write buffer
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*/
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ENTRY(v6_coherent_user_range)
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UNWIND(.fnstart )
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#ifdef HARVARD_CACHE
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bic r0, r0, #CACHE_LINE_SIZE - 1
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1:
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USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
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add r0, r0, #CACHE_LINE_SIZE
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2:
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cmp r0, r1
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blo 1b
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#endif
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mov r0, #0
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#ifdef HARVARD_CACHE
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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#ifndef CONFIG_ARM_ERRATA_411920
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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#else
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b v6_icache_inval_all
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#endif
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#else
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
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#endif
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mov pc, lr
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/*
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* Fault handling for the cache operation above. If the virtual address in r0
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* isn't mapped, just try the next page.
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*/
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9001:
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mov r0, r0, lsr #12
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mov r0, r0, lsl #12
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add r0, r0, #4096
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b 2b
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UNWIND(.fnend )
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ENDPROC(v6_coherent_user_range)
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ENDPROC(v6_coherent_kern_range)
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/*
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* v6_flush_kern_dcache_page(kaddr)
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*
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* Ensure that the data held in the page kaddr is written back
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* to the page in question.
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*
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* - kaddr - kernel address (guaranteed to be page aligned)
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*/
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ENTRY(v6_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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1:
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#ifdef HARVARD_CACHE
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mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
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#else
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mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
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#endif
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add r0, r0, #D_CACHE_LINE_SIZE
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cmp r0, r1
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blo 1b
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#ifdef HARVARD_CACHE
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4
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#endif
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mov pc, lr
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/*
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* v6_dma_inv_range(start,end)
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*
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* Invalidate the data cache within the specified region; we will
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* be performing a DMA operation in this region and we want to
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* purge old data in the cache.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(v6_dma_inv_range)
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tst r0, #D_CACHE_LINE_SIZE - 1
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bic r0, r0, #D_CACHE_LINE_SIZE - 1
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#ifdef HARVARD_CACHE
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mcrne p15, 0, r0, c7, c10, 1 @ clean D line
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#else
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mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
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#endif
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tst r1, #D_CACHE_LINE_SIZE - 1
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bic r1, r1, #D_CACHE_LINE_SIZE - 1
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#ifdef HARVARD_CACHE
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mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
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#else
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mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
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#endif
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1:
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#ifdef HARVARD_CACHE
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
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#else
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mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
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#endif
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add r0, r0, #D_CACHE_LINE_SIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mov pc, lr
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/*
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* v6_dma_clean_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(v6_dma_clean_range)
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bic r0, r0, #D_CACHE_LINE_SIZE - 1
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1:
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#ifdef HARVARD_CACHE
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mcr p15, 0, r0, c7, c10, 1 @ clean D line
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#else
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mcr p15, 0, r0, c7, c11, 1 @ clean unified line
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#endif
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add r0, r0, #D_CACHE_LINE_SIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mov pc, lr
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/*
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* v6_dma_flush_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(v6_dma_flush_range)
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bic r0, r0, #D_CACHE_LINE_SIZE - 1
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1:
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#ifdef HARVARD_CACHE
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mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
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#else
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mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
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#endif
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add r0, r0, #D_CACHE_LINE_SIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mov pc, lr
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__INITDATA
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.type v6_cache_fns, #object
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ENTRY(v6_cache_fns)
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.long v6_flush_kern_cache_all
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.long v6_flush_user_cache_all
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.long v6_flush_user_cache_range
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.long v6_coherent_kern_range
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.long v6_coherent_user_range
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.long v6_flush_kern_dcache_page
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.long v6_dma_inv_range
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.long v6_dma_clean_range
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.long v6_dma_flush_range
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.size v6_cache_fns, . - v6_cache_fns
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