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d050894435
This patch adds a cpuidle driver for systems based around the MIPS
Coherent Processing System (CPS) architecture. It supports four idle
states:
- The standard MIPS wait instruction.
- The non-coherent wait, clock gated & power gated states exposed by
the recently added pm-cps layer.
The pm-cps layer is used to enter all the deep idle states. Since cores
in the clock or power gated states cannot service interrupts, the
gic_send_ipi_single function is modified to send a power up command for
the appropriate core to the CPC in cases where the target CPU has marked
itself potentially incoherent.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
18 lines
592 B
Plaintext
18 lines
592 B
Plaintext
#
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# MIPS CPU Idle Drivers
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#
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config MIPS_CPS_CPUIDLE
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bool "CPU Idle driver for MIPS CPS platforms"
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depends on CPU_IDLE
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depends on SYS_SUPPORTS_MIPS_CPS
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select ARCH_NEEDS_CPU_IDLE_COUPLED if MIPS_MT
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select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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select MIPS_CPS_PM
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default y
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help
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Select this option to enable processor idle state management
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through cpuidle for systems built around the MIPS Coherent
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Processing System (CPS) architecture. In order to make use of
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the deepest idle states you will need to ensure that you are
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also using the CONFIG_MIPS_CPS SMP implementation.
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