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64c634ef83
Camcorders have a tendency to fail read requests to their config ROM and write request to their FCP command register with ack_busy_X. This has become a problem with newer kernels and especially Panasonic camcorders, causing AV/C in dvgrab and kino to fail. Dvgrab for example frequently logs "send oops"; kino reports loss of AV/C control. I suspect that lower CPU scheduling latencies in newer kernels made this issue more prominent now. According to https://sourceforge.net/tracker/?func=detail&atid=114103&aid=2492640&group_id=14103 this can be fixed by configuring the FireWire controller for more hardware retries for request transmission; these retries are evidently more successful than libavc1394's own retry loop (typically 3 tries on top of hardware retries). Presumably the same issue has been reported at https://bugzilla.redhat.com/show_bug.cgi?id=449252 and https://bugzilla.redhat.com/show_bug.cgi?id=477279 . Tested-by: Mathias Beilstein Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
454 lines
16 KiB
C
454 lines
16 KiB
C
/*
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* ohci1394.h - driver for OHCI 1394 boards
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* Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
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* Gord Peters <GordPeters@smarttech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _OHCI1394_H
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#define _OHCI1394_H
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#include "ieee1394_types.h"
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#include <asm/io.h>
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#define OHCI1394_DRIVER_NAME "ohci1394"
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#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
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#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
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#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
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#define OHCI1394_MAX_SELF_ID_ERRORS 16
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#define AR_REQ_NUM_DESC 4 /* number of AR req descriptors */
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#define AR_REQ_BUF_SIZE PAGE_SIZE /* size of AR req buffers */
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#define AR_REQ_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
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#define AR_RESP_NUM_DESC 4 /* number of AR resp descriptors */
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#define AR_RESP_BUF_SIZE PAGE_SIZE /* size of AR resp buffers */
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#define AR_RESP_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
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#define IR_NUM_DESC 16 /* number of IR descriptors */
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#define IR_BUF_SIZE PAGE_SIZE /* 4096 bytes/buffer */
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#define IR_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
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#define IT_NUM_DESC 16 /* number of IT descriptors */
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#define AT_REQ_NUM_DESC 32 /* number of AT req descriptors */
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#define AT_RESP_NUM_DESC 32 /* number of AT resp descriptors */
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#define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */
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#define OHCI_CONFIG_ROM_LEN 1024 /* Length of the mapped configrom space */
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#define OHCI1394_SI_DMA_BUF_SIZE 8192 /* length of the selfid buffer */
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/* PCI configuration space addresses */
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#define OHCI1394_PCI_HCI_Control 0x40
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struct dma_cmd {
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u32 control;
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u32 address;
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u32 branchAddress;
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u32 status;
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};
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/*
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* FIXME:
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* It is important that a single at_dma_prg does not cross a page boundary
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* The proper way to do it would be to do the check dynamically as the
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* programs are inserted into the AT fifo.
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*/
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struct at_dma_prg {
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struct dma_cmd begin;
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quadlet_t data[4];
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struct dma_cmd end;
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quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
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};
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/* identify whether a DMA context is asynchronous or isochronous */
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enum context_type { DMA_CTX_ASYNC_REQ, DMA_CTX_ASYNC_RESP, DMA_CTX_ISO };
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/* DMA receive context */
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struct dma_rcv_ctx {
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struct ti_ohci *ohci;
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enum context_type type;
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int ctx;
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unsigned int num_desc;
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unsigned int buf_size;
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unsigned int split_buf_size;
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/* dma block descriptors */
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struct dma_cmd **prg_cpu;
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dma_addr_t *prg_bus;
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struct pci_pool *prg_pool;
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/* dma buffers */
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quadlet_t **buf_cpu;
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dma_addr_t *buf_bus;
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unsigned int buf_ind;
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unsigned int buf_offset;
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quadlet_t *spb;
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spinlock_t lock;
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struct tasklet_struct task;
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int ctrlClear;
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int ctrlSet;
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int cmdPtr;
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int ctxtMatch;
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};
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/* DMA transmit context */
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struct dma_trm_ctx {
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struct ti_ohci *ohci;
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enum context_type type;
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int ctx;
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unsigned int num_desc;
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/* dma block descriptors */
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struct at_dma_prg **prg_cpu;
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dma_addr_t *prg_bus;
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struct pci_pool *prg_pool;
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unsigned int prg_ind;
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unsigned int sent_ind;
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int free_prgs;
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quadlet_t *branchAddrPtr;
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/* list of packets inserted in the AT FIFO */
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struct list_head fifo_list;
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/* list of pending packets to be inserted in the AT FIFO */
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struct list_head pending_list;
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spinlock_t lock;
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struct tasklet_struct task;
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int ctrlClear;
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int ctrlSet;
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int cmdPtr;
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};
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struct ohci1394_iso_tasklet {
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struct tasklet_struct tasklet;
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struct list_head link;
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int context;
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enum { OHCI_ISO_TRANSMIT, OHCI_ISO_RECEIVE,
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OHCI_ISO_MULTICHANNEL_RECEIVE } type;
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};
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struct ti_ohci {
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struct pci_dev *dev;
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enum {
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OHCI_INIT_ALLOC_HOST,
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OHCI_INIT_HAVE_MEM_REGION,
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OHCI_INIT_HAVE_IOMAPPING,
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OHCI_INIT_HAVE_CONFIG_ROM_BUFFER,
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OHCI_INIT_HAVE_SELFID_BUFFER,
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OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE,
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OHCI_INIT_HAVE_IRQ,
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OHCI_INIT_DONE,
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} init_state;
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/* remapped memory spaces */
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void __iomem *registers;
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/* dma buffer for self-id packets */
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quadlet_t *selfid_buf_cpu;
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dma_addr_t selfid_buf_bus;
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/* buffer for csr config rom */
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quadlet_t *csr_config_rom_cpu;
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dma_addr_t csr_config_rom_bus;
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int csr_config_rom_length;
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unsigned int max_packet_size;
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/* async receive */
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struct dma_rcv_ctx ar_resp_context;
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struct dma_rcv_ctx ar_req_context;
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/* async transmit */
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struct dma_trm_ctx at_resp_context;
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struct dma_trm_ctx at_req_context;
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/* iso receive */
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int nb_iso_rcv_ctx;
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unsigned long ir_ctx_usage; /* use test_and_set_bit() for atomicity */
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unsigned long ir_multichannel_used; /* ditto */
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spinlock_t IR_channel_lock;
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/* iso transmit */
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int nb_iso_xmit_ctx;
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unsigned long it_ctx_usage; /* use test_and_set_bit() for atomicity */
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u64 ISO_channel_usage;
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/* IEEE-1394 part follows */
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struct hpsb_host *host;
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int phyid, isroot;
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spinlock_t phy_reg_lock;
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spinlock_t event_lock;
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int self_id_errors;
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/* Tasklets for iso receive and transmit, used by video1394
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* and dv1394 */
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struct list_head iso_tasklet_list;
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spinlock_t iso_tasklet_list_lock;
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/* Swap the selfid buffer? */
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unsigned int selfid_swap:1;
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/* Some Apple chipset seem to swap incoming headers for us */
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unsigned int no_swap_incoming:1;
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/* Force extra paranoia checking on bus-reset handling */
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unsigned int check_busreset:1;
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};
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static inline int cross_bound(unsigned long addr, unsigned int size)
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{
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if (size == 0)
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return 0;
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if (size > PAGE_SIZE)
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return 1;
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if (addr >> PAGE_SHIFT != (addr + size - 1) >> PAGE_SHIFT)
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return 1;
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return 0;
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}
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/*
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* Register read and write helper functions.
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*/
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static inline void reg_write(const struct ti_ohci *ohci, int offset, u32 data)
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{
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writel(data, ohci->registers + offset);
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}
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static inline u32 reg_read(const struct ti_ohci *ohci, int offset)
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{
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return readl(ohci->registers + offset);
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}
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/* 2 KiloBytes of register space */
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#define OHCI1394_REGISTER_SIZE 0x800
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/* Offsets relative to context bases defined below */
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#define OHCI1394_ContextControlSet 0x000
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#define OHCI1394_ContextControlClear 0x004
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#define OHCI1394_ContextCommandPtr 0x00C
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/* register map */
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#define OHCI1394_Version 0x000
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#define OHCI1394_GUID_ROM 0x004
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#define OHCI1394_ATRetries 0x008
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#define OHCI1394_CSRData 0x00C
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#define OHCI1394_CSRCompareData 0x010
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#define OHCI1394_CSRControl 0x014
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#define OHCI1394_ConfigROMhdr 0x018
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#define OHCI1394_BusID 0x01C
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#define OHCI1394_BusOptions 0x020
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#define OHCI1394_GUIDHi 0x024
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#define OHCI1394_GUIDLo 0x028
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#define OHCI1394_ConfigROMmap 0x034
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#define OHCI1394_PostedWriteAddressLo 0x038
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#define OHCI1394_PostedWriteAddressHi 0x03C
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#define OHCI1394_VendorID 0x040
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#define OHCI1394_HCControlSet 0x050
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#define OHCI1394_HCControlClear 0x054
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#define OHCI1394_HCControl_noByteSwap 0x40000000
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#define OHCI1394_HCControl_programPhyEnable 0x00800000
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#define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000
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#define OHCI1394_HCControl_LPS 0x00080000
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#define OHCI1394_HCControl_postedWriteEnable 0x00040000
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#define OHCI1394_HCControl_linkEnable 0x00020000
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#define OHCI1394_HCControl_softReset 0x00010000
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#define OHCI1394_SelfIDBuffer 0x064
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#define OHCI1394_SelfIDCount 0x068
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#define OHCI1394_IRMultiChanMaskHiSet 0x070
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#define OHCI1394_IRMultiChanMaskHiClear 0x074
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#define OHCI1394_IRMultiChanMaskLoSet 0x078
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#define OHCI1394_IRMultiChanMaskLoClear 0x07C
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#define OHCI1394_IntEventSet 0x080
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#define OHCI1394_IntEventClear 0x084
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#define OHCI1394_IntMaskSet 0x088
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#define OHCI1394_IntMaskClear 0x08C
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#define OHCI1394_IsoXmitIntEventSet 0x090
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#define OHCI1394_IsoXmitIntEventClear 0x094
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#define OHCI1394_IsoXmitIntMaskSet 0x098
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#define OHCI1394_IsoXmitIntMaskClear 0x09C
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#define OHCI1394_IsoRecvIntEventSet 0x0A0
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#define OHCI1394_IsoRecvIntEventClear 0x0A4
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#define OHCI1394_IsoRecvIntMaskSet 0x0A8
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#define OHCI1394_IsoRecvIntMaskClear 0x0AC
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#define OHCI1394_InitialBandwidthAvailable 0x0B0
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#define OHCI1394_InitialChannelsAvailableHi 0x0B4
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#define OHCI1394_InitialChannelsAvailableLo 0x0B8
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#define OHCI1394_FairnessControl 0x0DC
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#define OHCI1394_LinkControlSet 0x0E0
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#define OHCI1394_LinkControlClear 0x0E4
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#define OHCI1394_LinkControl_RcvSelfID 0x00000200
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#define OHCI1394_LinkControl_RcvPhyPkt 0x00000400
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#define OHCI1394_LinkControl_CycleTimerEnable 0x00100000
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#define OHCI1394_LinkControl_CycleMaster 0x00200000
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#define OHCI1394_LinkControl_CycleSource 0x00400000
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#define OHCI1394_NodeID 0x0E8
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#define OHCI1394_PhyControl 0x0EC
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#define OHCI1394_IsochronousCycleTimer 0x0F0
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#define OHCI1394_AsReqFilterHiSet 0x100
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#define OHCI1394_AsReqFilterHiClear 0x104
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#define OHCI1394_AsReqFilterLoSet 0x108
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#define OHCI1394_AsReqFilterLoClear 0x10C
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#define OHCI1394_PhyReqFilterHiSet 0x110
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#define OHCI1394_PhyReqFilterHiClear 0x114
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#define OHCI1394_PhyReqFilterLoSet 0x118
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#define OHCI1394_PhyReqFilterLoClear 0x11C
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#define OHCI1394_PhyUpperBound 0x120
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#define OHCI1394_AsReqTrContextBase 0x180
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#define OHCI1394_AsReqTrContextControlSet 0x180
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#define OHCI1394_AsReqTrContextControlClear 0x184
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#define OHCI1394_AsReqTrCommandPtr 0x18C
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#define OHCI1394_AsRspTrContextBase 0x1A0
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#define OHCI1394_AsRspTrContextControlSet 0x1A0
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#define OHCI1394_AsRspTrContextControlClear 0x1A4
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#define OHCI1394_AsRspTrCommandPtr 0x1AC
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#define OHCI1394_AsReqRcvContextBase 0x1C0
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#define OHCI1394_AsReqRcvContextControlSet 0x1C0
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#define OHCI1394_AsReqRcvContextControlClear 0x1C4
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#define OHCI1394_AsReqRcvCommandPtr 0x1CC
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#define OHCI1394_AsRspRcvContextBase 0x1E0
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#define OHCI1394_AsRspRcvContextControlSet 0x1E0
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#define OHCI1394_AsRspRcvContextControlClear 0x1E4
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#define OHCI1394_AsRspRcvCommandPtr 0x1EC
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/* Isochronous transmit registers */
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/* Add (16 * n) for context n */
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#define OHCI1394_IsoXmitContextBase 0x200
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#define OHCI1394_IsoXmitContextControlSet 0x200
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#define OHCI1394_IsoXmitContextControlClear 0x204
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#define OHCI1394_IsoXmitCommandPtr 0x20C
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/* Isochronous receive registers */
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/* Add (32 * n) for context n */
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#define OHCI1394_IsoRcvContextBase 0x400
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#define OHCI1394_IsoRcvContextControlSet 0x400
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#define OHCI1394_IsoRcvContextControlClear 0x404
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#define OHCI1394_IsoRcvCommandPtr 0x40C
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#define OHCI1394_IsoRcvContextMatch 0x410
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/* Interrupts Mask/Events */
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#define OHCI1394_reqTxComplete 0x00000001
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#define OHCI1394_respTxComplete 0x00000002
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#define OHCI1394_ARRQ 0x00000004
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#define OHCI1394_ARRS 0x00000008
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#define OHCI1394_RQPkt 0x00000010
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#define OHCI1394_RSPkt 0x00000020
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#define OHCI1394_isochTx 0x00000040
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#define OHCI1394_isochRx 0x00000080
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#define OHCI1394_postedWriteErr 0x00000100
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#define OHCI1394_lockRespErr 0x00000200
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#define OHCI1394_selfIDComplete 0x00010000
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#define OHCI1394_busReset 0x00020000
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#define OHCI1394_phy 0x00080000
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#define OHCI1394_cycleSynch 0x00100000
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#define OHCI1394_cycle64Seconds 0x00200000
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#define OHCI1394_cycleLost 0x00400000
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#define OHCI1394_cycleInconsistent 0x00800000
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#define OHCI1394_unrecoverableError 0x01000000
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#define OHCI1394_cycleTooLong 0x02000000
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#define OHCI1394_phyRegRcvd 0x04000000
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#define OHCI1394_masterIntEnable 0x80000000
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/* DMA Control flags */
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#define DMA_CTL_OUTPUT_MORE 0x00000000
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#define DMA_CTL_OUTPUT_LAST 0x10000000
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#define DMA_CTL_INPUT_MORE 0x20000000
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#define DMA_CTL_INPUT_LAST 0x30000000
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#define DMA_CTL_UPDATE 0x08000000
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#define DMA_CTL_IMMEDIATE 0x02000000
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#define DMA_CTL_IRQ 0x00300000
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#define DMA_CTL_BRANCH 0x000c0000
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#define DMA_CTL_WAIT 0x00030000
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/* OHCI evt_* error types, table 3-2 of the OHCI 1.1 spec. */
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#define EVT_NO_STATUS 0x0 /* No event status */
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#define EVT_RESERVED_A 0x1 /* Reserved, not used !!! */
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#define EVT_LONG_PACKET 0x2 /* The revc data was longer than the buf */
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#define EVT_MISSING_ACK 0x3 /* A subaction gap was detected before an ack
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arrived, or recv'd ack had a parity error */
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#define EVT_UNDERRUN 0x4 /* Underrun on corresponding FIFO, packet
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truncated */
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#define EVT_OVERRUN 0x5 /* A recv FIFO overflowed on reception of ISO
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packet */
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#define EVT_DESCRIPTOR_READ 0x6 /* An unrecoverable error occurred while host was
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reading a descriptor block */
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#define EVT_DATA_READ 0x7 /* An error occurred while host controller was
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attempting to read from host memory in the data
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stage of descriptor processing */
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#define EVT_DATA_WRITE 0x8 /* An error occurred while host controller was
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attempting to write either during the data stage
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of descriptor processing, or when processing a single
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16-bit host memory write */
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#define EVT_BUS_RESET 0x9 /* Identifies a PHY packet in the recv buffer as
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being a synthesized bus reset packet */
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#define EVT_TIMEOUT 0xa /* Indicates that the asynchronous transmit response
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packet expired and was not transmitted, or that an
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IT DMA context experienced a skip processing overflow */
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#define EVT_TCODE_ERR 0xb /* A bad tCode is associated with this packet.
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The packet was flushed */
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#define EVT_RESERVED_B 0xc /* Reserved, not used !!! */
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#define EVT_RESERVED_C 0xd /* Reserved, not used !!! */
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#define EVT_UNKNOWN 0xe /* An error condition has occurred that cannot be
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represented by any other event codes defined herein. */
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#define EVT_FLUSHED 0xf /* Send by the link side of output FIFO when asynchronous
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packets are being flushed due to a bus reset. */
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#define OHCI1394_TCODE_PHY 0xE
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/* Node offset map (phys DMA area, posted write area).
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* The value of OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED may be modified but must
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* be lower than OHCI1394_MIDDLE_ADDRESS_SPACE.
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* OHCI1394_PHYS_UPPER_BOUND_FIXED and OHCI1394_MIDDLE_ADDRESS_SPACE are
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* constants given by the OHCI spec.
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*/
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#define OHCI1394_PHYS_UPPER_BOUND_FIXED 0x000100000000ULL /* 4 GB */
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#define OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED 0x010000000000ULL /* 1 TB */
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#define OHCI1394_MIDDLE_ADDRESS_SPACE 0xffff00000000ULL
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void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet,
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int type,
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void (*func)(unsigned long),
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unsigned long data);
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int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
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struct ohci1394_iso_tasklet *tasklet);
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void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
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struct ohci1394_iso_tasklet *tasklet);
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int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg);
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struct ti_ohci *ohci1394_get_struct(int card_num);
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#endif
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