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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
538 lines
12 KiB
C
538 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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*
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* Copyright (C) 2007 Alan Stern
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* Copyright (C) 2009 IBM Corporation
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* Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
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*
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* Authors: Alan Stern <stern@rowland.harvard.edu>
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* K.Prasad <prasad@linux.vnet.ibm.com>
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* Frederic Weisbecker <fweisbec@gmail.com>
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*/
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/*
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* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
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* using the CPU's debug registers.
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*/
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#include <linux/perf_event.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/irqflags.h>
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#include <linux/notifier.h>
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#include <linux/kallsyms.h>
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#include <linux/kprobes.h>
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#include <linux/percpu.h>
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#include <linux/kdebug.h>
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/processor.h>
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#include <asm/debugreg.h>
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#include <asm/user.h>
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/* Per cpu debug control register value */
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DEFINE_PER_CPU(unsigned long, cpu_dr7);
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EXPORT_PER_CPU_SYMBOL(cpu_dr7);
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/* Per cpu debug address registers values */
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static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);
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/*
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* Stores the breakpoints currently in use on each breakpoint address
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* register for each cpus
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*/
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static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
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static inline unsigned long
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__encode_dr7(int drnum, unsigned int len, unsigned int type)
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{
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unsigned long bp_info;
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bp_info = (len | type) & 0xf;
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bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
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bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));
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return bp_info;
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}
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/*
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* Encode the length, type, Exact, and Enable bits for a particular breakpoint
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* as stored in debug register 7.
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*/
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unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
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{
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return __encode_dr7(drnum, len, type) | DR_GLOBAL_SLOWDOWN;
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}
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/*
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* Decode the length and type bits for a particular breakpoint as
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* stored in debug register 7. Return the "enabled" status.
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*/
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int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type)
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{
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int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
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*len = (bp_info & 0xc) | 0x40;
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*type = (bp_info & 0x3) | 0x80;
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return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
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}
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/*
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* Install a perf counter breakpoint.
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*
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* We seek a free debug address register and use it for this
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* breakpoint. Eventually we enable it in the debug control register.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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int arch_install_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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unsigned long *dr7;
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int i;
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for (i = 0; i < HBP_NUM; i++) {
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struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
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if (!*slot) {
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*slot = bp;
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break;
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}
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}
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if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
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return -EBUSY;
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set_debugreg(info->address, i);
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__this_cpu_write(cpu_debugreg[i], info->address);
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dr7 = this_cpu_ptr(&cpu_dr7);
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*dr7 |= encode_dr7(i, info->len, info->type);
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set_debugreg(*dr7, 7);
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if (info->mask)
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set_dr_addr_mask(info->mask, i);
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return 0;
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}
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/*
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* Uninstall the breakpoint contained in the given counter.
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*
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* First we search the debug address register it uses and then we disable
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* it.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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void arch_uninstall_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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unsigned long *dr7;
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int i;
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for (i = 0; i < HBP_NUM; i++) {
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struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
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if (*slot == bp) {
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*slot = NULL;
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break;
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}
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}
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if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
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return;
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dr7 = this_cpu_ptr(&cpu_dr7);
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*dr7 &= ~__encode_dr7(i, info->len, info->type);
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set_debugreg(*dr7, 7);
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if (info->mask)
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set_dr_addr_mask(0, i);
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}
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static int arch_bp_generic_len(int x86_len)
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{
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switch (x86_len) {
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case X86_BREAKPOINT_LEN_1:
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return HW_BREAKPOINT_LEN_1;
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case X86_BREAKPOINT_LEN_2:
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return HW_BREAKPOINT_LEN_2;
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case X86_BREAKPOINT_LEN_4:
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return HW_BREAKPOINT_LEN_4;
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#ifdef CONFIG_X86_64
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case X86_BREAKPOINT_LEN_8:
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return HW_BREAKPOINT_LEN_8;
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#endif
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default:
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return -EINVAL;
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}
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}
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int arch_bp_generic_fields(int x86_len, int x86_type,
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int *gen_len, int *gen_type)
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{
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int len;
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/* Type */
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switch (x86_type) {
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case X86_BREAKPOINT_EXECUTE:
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if (x86_len != X86_BREAKPOINT_LEN_X)
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return -EINVAL;
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*gen_type = HW_BREAKPOINT_X;
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*gen_len = sizeof(long);
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return 0;
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case X86_BREAKPOINT_WRITE:
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*gen_type = HW_BREAKPOINT_W;
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break;
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case X86_BREAKPOINT_RW:
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*gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
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break;
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default:
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return -EINVAL;
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}
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/* Len */
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len = arch_bp_generic_len(x86_len);
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if (len < 0)
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return -EINVAL;
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*gen_len = len;
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return 0;
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}
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/*
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* Check for virtual address in kernel space.
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*/
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int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
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{
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unsigned long va;
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int len;
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va = hw->address;
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len = arch_bp_generic_len(hw->len);
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WARN_ON_ONCE(len < 0);
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/*
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* We don't need to worry about va + len - 1 overflowing:
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* we already require that va is aligned to a multiple of len.
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*/
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return (va >= TASK_SIZE_MAX) || ((va + len - 1) >= TASK_SIZE_MAX);
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}
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static int arch_build_bp_info(struct perf_event *bp,
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const struct perf_event_attr *attr,
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struct arch_hw_breakpoint *hw)
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{
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hw->address = attr->bp_addr;
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hw->mask = 0;
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/* Type */
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switch (attr->bp_type) {
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case HW_BREAKPOINT_W:
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hw->type = X86_BREAKPOINT_WRITE;
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break;
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case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
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hw->type = X86_BREAKPOINT_RW;
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break;
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case HW_BREAKPOINT_X:
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/*
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* We don't allow kernel breakpoints in places that are not
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* acceptable for kprobes. On non-kprobes kernels, we don't
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* allow kernel breakpoints at all.
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*/
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if (attr->bp_addr >= TASK_SIZE_MAX) {
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if (within_kprobe_blacklist(attr->bp_addr))
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return -EINVAL;
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}
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hw->type = X86_BREAKPOINT_EXECUTE;
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/*
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* x86 inst breakpoints need to have a specific undefined len.
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* But we still need to check userspace is not trying to setup
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* an unsupported length, to get a range breakpoint for example.
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*/
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if (attr->bp_len == sizeof(long)) {
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hw->len = X86_BREAKPOINT_LEN_X;
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return 0;
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}
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/* fall through */
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default:
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return -EINVAL;
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}
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/* Len */
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switch (attr->bp_len) {
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case HW_BREAKPOINT_LEN_1:
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hw->len = X86_BREAKPOINT_LEN_1;
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break;
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case HW_BREAKPOINT_LEN_2:
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hw->len = X86_BREAKPOINT_LEN_2;
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break;
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case HW_BREAKPOINT_LEN_4:
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hw->len = X86_BREAKPOINT_LEN_4;
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break;
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#ifdef CONFIG_X86_64
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case HW_BREAKPOINT_LEN_8:
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hw->len = X86_BREAKPOINT_LEN_8;
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break;
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#endif
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default:
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/* AMD range breakpoint */
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if (!is_power_of_2(attr->bp_len))
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return -EINVAL;
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if (attr->bp_addr & (attr->bp_len - 1))
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return -EINVAL;
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if (!boot_cpu_has(X86_FEATURE_BPEXT))
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return -EOPNOTSUPP;
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/*
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* It's impossible to use a range breakpoint to fake out
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* user vs kernel detection because bp_len - 1 can't
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* have the high bit set. If we ever allow range instruction
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* breakpoints, then we'll have to check for kprobe-blacklisted
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* addresses anywhere in the range.
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*/
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hw->mask = attr->bp_len - 1;
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hw->len = X86_BREAKPOINT_LEN_1;
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}
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return 0;
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}
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/*
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* Validate the arch-specific HW Breakpoint register settings
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*/
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int hw_breakpoint_arch_parse(struct perf_event *bp,
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const struct perf_event_attr *attr,
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struct arch_hw_breakpoint *hw)
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{
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unsigned int align;
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int ret;
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ret = arch_build_bp_info(bp, attr, hw);
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if (ret)
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return ret;
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switch (hw->len) {
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case X86_BREAKPOINT_LEN_1:
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align = 0;
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if (hw->mask)
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align = hw->mask;
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break;
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case X86_BREAKPOINT_LEN_2:
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align = 1;
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break;
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case X86_BREAKPOINT_LEN_4:
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align = 3;
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break;
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#ifdef CONFIG_X86_64
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case X86_BREAKPOINT_LEN_8:
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align = 7;
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break;
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#endif
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default:
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WARN_ON_ONCE(1);
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return -EINVAL;
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}
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/*
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* Check that the low-order bits of the address are appropriate
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* for the alignment implied by len.
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*/
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if (hw->address & align)
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return -EINVAL;
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return 0;
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}
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/*
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* Dump the debug register contents to the user.
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* We can't dump our per cpu values because it
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* may contain cpu wide breakpoint, something that
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* doesn't belong to the current task.
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*
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* TODO: include non-ptrace user breakpoints (perf)
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*/
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void aout_dump_debugregs(struct user *dump)
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{
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int i;
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int dr7 = 0;
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struct perf_event *bp;
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struct arch_hw_breakpoint *info;
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struct thread_struct *thread = ¤t->thread;
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for (i = 0; i < HBP_NUM; i++) {
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bp = thread->ptrace_bps[i];
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if (bp && !bp->attr.disabled) {
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dump->u_debugreg[i] = bp->attr.bp_addr;
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info = counter_arch_bp(bp);
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dr7 |= encode_dr7(i, info->len, info->type);
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} else {
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dump->u_debugreg[i] = 0;
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}
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}
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dump->u_debugreg[4] = 0;
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dump->u_debugreg[5] = 0;
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dump->u_debugreg[6] = current->thread.debugreg6;
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dump->u_debugreg[7] = dr7;
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}
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EXPORT_SYMBOL_GPL(aout_dump_debugregs);
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/*
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* Release the user breakpoints used by ptrace
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*/
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void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
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{
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int i;
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struct thread_struct *t = &tsk->thread;
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for (i = 0; i < HBP_NUM; i++) {
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unregister_hw_breakpoint(t->ptrace_bps[i]);
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t->ptrace_bps[i] = NULL;
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}
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t->debugreg6 = 0;
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t->ptrace_dr7 = 0;
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}
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void hw_breakpoint_restore(void)
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{
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set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
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set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
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set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
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set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
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set_debugreg(current->thread.debugreg6, 6);
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set_debugreg(__this_cpu_read(cpu_dr7), 7);
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}
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EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
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/*
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* Handle debug exception notifications.
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*
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* Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
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*
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* NOTIFY_DONE returned if one of the following conditions is true.
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* i) When the causative address is from user-space and the exception
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* is a valid one, i.e. not triggered as a result of lazy debug register
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* switching
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* ii) When there are more bits than trap<n> set in DR6 register (such
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* as BD, BS or BT) indicating that more than one debug condition is
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* met and requires some more action in do_debug().
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*
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* NOTIFY_STOP returned for all other cases
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*
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*/
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static int hw_breakpoint_handler(struct die_args *args)
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{
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int i, cpu, rc = NOTIFY_STOP;
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struct perf_event *bp;
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unsigned long dr7, dr6;
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unsigned long *dr6_p;
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/* The DR6 value is pointed by args->err */
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dr6_p = (unsigned long *)ERR_PTR(args->err);
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dr6 = *dr6_p;
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/* If it's a single step, TRAP bits are random */
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if (dr6 & DR_STEP)
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return NOTIFY_DONE;
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/* Do an early return if no trap bits are set in DR6 */
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if ((dr6 & DR_TRAP_BITS) == 0)
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return NOTIFY_DONE;
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get_debugreg(dr7, 7);
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/* Disable breakpoints during exception handling */
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set_debugreg(0UL, 7);
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/*
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* Assert that local interrupts are disabled
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* Reset the DRn bits in the virtualized register value.
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* The ptrace trigger routine will add in whatever is needed.
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*/
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current->thread.debugreg6 &= ~DR_TRAP_BITS;
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cpu = get_cpu();
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/* Handle all the breakpoints that were triggered */
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for (i = 0; i < HBP_NUM; ++i) {
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if (likely(!(dr6 & (DR_TRAP0 << i))))
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continue;
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/*
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* The counter may be concurrently released but that can only
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* occur from a call_rcu() path. We can then safely fetch
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* the breakpoint, use its callback, touch its counter
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* while we are in an rcu_read_lock() path.
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*/
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rcu_read_lock();
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bp = per_cpu(bp_per_reg[i], cpu);
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/*
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* Reset the 'i'th TRAP bit in dr6 to denote completion of
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* exception handling
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*/
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(*dr6_p) &= ~(DR_TRAP0 << i);
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/*
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* bp can be NULL due to lazy debug register switching
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* or due to concurrent perf counter removing.
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*/
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if (!bp) {
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rcu_read_unlock();
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break;
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}
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perf_bp_event(bp, args->regs);
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/*
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* Set up resume flag to avoid breakpoint recursion when
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* returning back to origin.
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*/
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if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
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args->regs->flags |= X86_EFLAGS_RF;
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rcu_read_unlock();
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}
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/*
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* Further processing in do_debug() is needed for a) user-space
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* breakpoints (to generate signals) and b) when the system has
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* taken exception due to multiple causes
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*/
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if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
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(dr6 & (~DR_TRAP_BITS)))
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rc = NOTIFY_DONE;
|
|
|
|
set_debugreg(dr7, 7);
|
|
put_cpu();
|
|
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* Handle debug exception notifications.
|
|
*/
|
|
int hw_breakpoint_exceptions_notify(
|
|
struct notifier_block *unused, unsigned long val, void *data)
|
|
{
|
|
if (val != DIE_DEBUG)
|
|
return NOTIFY_DONE;
|
|
|
|
return hw_breakpoint_handler(data);
|
|
}
|
|
|
|
void hw_breakpoint_pmu_read(struct perf_event *bp)
|
|
{
|
|
/* TODO */
|
|
}
|