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a8811ec764
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974 that has KRAIT processors the voltage/current value of each OPP varies based on the silicon variant in use. The required OPP related data is determined based on the efuse value. This is similar to the existing code for kryo cores. So adding support for krait cores here. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
797 lines
20 KiB
Plaintext
797 lines
20 KiB
Plaintext
Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
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===================================
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In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,
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the CPU frequencies subset and voltage value of each OPP varies based on
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the silicon variant in use.
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Qualcomm Technologies, Inc. Process Voltage Scaling Tables
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defines the voltage and frequency value based on the msm-id in SMEM
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and speedbin blown in the efuse combination.
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The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
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to provide the OPP framework with required information (existing HW bitmap).
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This is used to determine the voltage and frequency value for each OPP of
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operating-points-v2 table when it is parsed by the OPP framework.
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Required properties:
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--------------------
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In 'cpu' nodes:
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- operating-points-v2: Phandle to the operating-points-v2 table to use.
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In 'operating-points-v2' table:
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- compatible: Should be
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- 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
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apq8064, ipq8064, msm8960 and ipq8074.
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Optional properties:
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--------------------
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In 'cpu' nodes:
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- power-domains: A phandle pointing to the PM domain specifier which provides
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the performance states available for active state management.
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Please refer to the power-domains bindings
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Documentation/devicetree/bindings/power/power_domain.txt
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and also examples below.
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- power-domain-names: Should be
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- 'cpr' for qcs404.
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In 'operating-points-v2' table:
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- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
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efuse registers that has information about the
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speedbin that is used to select the right frequency/voltage
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value pair.
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Please refer the for nvmem-cells
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bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
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and also examples below.
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In every OPP node:
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- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
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Bitmap:
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0: MSM8996 V3, speedbin 0
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1: MSM8996 V3, speedbin 1
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2: MSM8996 V3, speedbin 2
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3: unused
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4: MSM8996 SG, speedbin 0
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5: MSM8996 SG, speedbin 1
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6: MSM8996 SG, speedbin 2
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7-31: unused
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Example 1:
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---------
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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clocks = <&kryocc 0>;
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cpu-supply = <&pm8994_s11_saw>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x1>;
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enable-method = "psci";
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clocks = <&kryocc 0>;
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cpu-supply = <&pm8994_s11_saw>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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clocks = <&kryocc 1>;
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cpu-supply = <&pm8994_s11_saw>;
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operating-points-v2 = <&cluster1_opp>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x101>;
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enable-method = "psci";
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clocks = <&kryocc 1>;
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cpu-supply = <&pm8994_s11_saw>;
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operating-points-v2 = <&cluster1_opp>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2-kryo-cpu";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp-307200000 {
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opp-hz = /bits/ 64 <307200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x77>;
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clock-latency-ns = <200000>;
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};
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opp-384000000 {
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opp-hz = /bits/ 64 <384000000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-422400000 {
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opp-hz = /bits/ 64 <422400000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-460800000 {
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opp-hz = /bits/ 64 <460800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-480000000 {
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-537600000 {
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opp-hz = /bits/ 64 <537600000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-556800000 {
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opp-hz = /bits/ 64 <556800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-614400000 {
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opp-hz = /bits/ 64 <614400000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-652800000 {
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opp-hz = /bits/ 64 <652800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-691200000 {
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opp-hz = /bits/ 64 <691200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-729600000 {
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opp-hz = /bits/ 64 <729600000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-768000000 {
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opp-hz = /bits/ 64 <768000000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-844800000 {
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opp-hz = /bits/ 64 <844800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x77>;
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clock-latency-ns = <200000>;
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};
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opp-902400000 {
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opp-hz = /bits/ 64 <902400000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-960000000 {
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opp-hz = /bits/ 64 <960000000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-979200000 {
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opp-hz = /bits/ 64 <979200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-1036800000 {
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opp-hz = /bits/ 64 <1036800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-1113600000 {
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opp-hz = /bits/ 64 <1113600000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-1132800000 {
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opp-hz = /bits/ 64 <1132800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-1190400000 {
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opp-hz = /bits/ 64 <1190400000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-1209600000 {
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opp-hz = /bits/ 64 <1209600000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-1228800000 {
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opp-hz = /bits/ 64 <1228800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-1286400000 {
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opp-hz = /bits/ 64 <1286400000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-1324800000 {
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opp-hz = /bits/ 64 <1324800000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x5>;
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clock-latency-ns = <200000>;
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};
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opp-1363200000 {
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opp-hz = /bits/ 64 <1363200000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x72>;
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clock-latency-ns = <200000>;
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};
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opp-1401600000 {
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opp-hz = /bits/ 64 <1401600000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x5>;
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clock-latency-ns = <200000>;
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};
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opp-1440000000 {
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opp-hz = /bits/ 64 <1440000000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-1478400000 {
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opp-hz = /bits/ 64 <1478400000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x1>;
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clock-latency-ns = <200000>;
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};
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opp-1497600000 {
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opp-hz = /bits/ 64 <1497600000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x4>;
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clock-latency-ns = <200000>;
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};
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opp-1516800000 {
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opp-hz = /bits/ 64 <1516800000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-1593600000 {
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opp-hz = /bits/ 64 <1593600000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x71>;
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clock-latency-ns = <200000>;
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};
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opp-1996800000 {
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opp-hz = /bits/ 64 <1996800000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x20>;
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clock-latency-ns = <200000>;
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};
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opp-2188800000 {
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opp-hz = /bits/ 64 <2188800000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x10>;
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clock-latency-ns = <200000>;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2-kryo-cpu";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp-307200000 {
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opp-hz = /bits/ 64 <307200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x77>;
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clock-latency-ns = <200000>;
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};
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opp-384000000 {
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opp-hz = /bits/ 64 <384000000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-403200000 {
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opp-hz = /bits/ 64 <403200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-460800000 {
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opp-hz = /bits/ 64 <460800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-480000000 {
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-537600000 {
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opp-hz = /bits/ 64 <537600000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-556800000 {
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opp-hz = /bits/ 64 <556800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-614400000 {
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opp-hz = /bits/ 64 <614400000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-652800000 {
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opp-hz = /bits/ 64 <652800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-691200000 {
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opp-hz = /bits/ 64 <691200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-729600000 {
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opp-hz = /bits/ 64 <729600000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-748800000 {
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opp-hz = /bits/ 64 <748800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-806400000 {
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opp-hz = /bits/ 64 <806400000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-825600000 {
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opp-hz = /bits/ 64 <825600000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-883200000 {
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opp-hz = /bits/ 64 <883200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-902400000 {
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opp-hz = /bits/ 64 <902400000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-940800000 {
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opp-hz = /bits/ 64 <940800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-979200000 {
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opp-hz = /bits/ 64 <979200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-1036800000 {
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opp-hz = /bits/ 64 <1036800000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
|
|
};
|
|
opp-1056000000 {
|
|
opp-hz = /bits/ 64 <1056000000>;
|
|
opp-microvolt = <905000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1113600000 {
|
|
opp-hz = /bits/ 64 <1113600000>;
|
|
opp-microvolt = <905000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1132800000 {
|
|
opp-hz = /bits/ 64 <1132800000>;
|
|
opp-microvolt = <905000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1190400000 {
|
|
opp-hz = /bits/ 64 <1190400000>;
|
|
opp-microvolt = <905000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1209600000 {
|
|
opp-hz = /bits/ 64 <1209600000>;
|
|
opp-microvolt = <905000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1248000000 {
|
|
opp-hz = /bits/ 64 <1248000000>;
|
|
opp-microvolt = <905000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1286400000 {
|
|
opp-hz = /bits/ 64 <1286400000>;
|
|
opp-microvolt = <905000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1324800000 {
|
|
opp-hz = /bits/ 64 <1324800000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1363200000 {
|
|
opp-hz = /bits/ 64 <1363200000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1401600000 {
|
|
opp-hz = /bits/ 64 <1401600000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1440000000 {
|
|
opp-hz = /bits/ 64 <1440000000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1478400000 {
|
|
opp-hz = /bits/ 64 <1478400000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1516800000 {
|
|
opp-hz = /bits/ 64 <1516800000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1555200000 {
|
|
opp-hz = /bits/ 64 <1555200000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1593600000 {
|
|
opp-hz = /bits/ 64 <1593600000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1632000000 {
|
|
opp-hz = /bits/ 64 <1632000000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1670400000 {
|
|
opp-hz = /bits/ 64 <1670400000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1708800000 {
|
|
opp-hz = /bits/ 64 <1708800000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1747200000 {
|
|
opp-hz = /bits/ 64 <1747200000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x70>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1785600000 {
|
|
opp-hz = /bits/ 64 <1785600000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x7>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1804800000 {
|
|
opp-hz = /bits/ 64 <1804800000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x6>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1824000000 {
|
|
opp-hz = /bits/ 64 <1824000000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x71>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1900800000 {
|
|
opp-hz = /bits/ 64 <1900800000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x74>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1920000000 {
|
|
opp-hz = /bits/ 64 <1920000000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x1>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1977600000 {
|
|
opp-hz = /bits/ 64 <1977600000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x30>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-1996800000 {
|
|
opp-hz = /bits/ 64 <1996800000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x1>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-2054400000 {
|
|
opp-hz = /bits/ 64 <2054400000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x30>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-2073600000 {
|
|
opp-hz = /bits/ 64 <2073600000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x1>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-2150400000 {
|
|
opp-hz = /bits/ 64 <2150400000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x31>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-2246400000 {
|
|
opp-hz = /bits/ 64 <2246400000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x10>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
opp-2342400000 {
|
|
opp-hz = /bits/ 64 <2342400000>;
|
|
opp-microvolt = <1140000 905000 1140000>;
|
|
opp-supported-hw = <0x10>;
|
|
clock-latency-ns = <200000>;
|
|
};
|
|
};
|
|
|
|
....
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
....
|
|
smem_mem: smem-mem@86000000 {
|
|
reg = <0x0 0x86000000 0x0 0x200000>;
|
|
no-map;
|
|
};
|
|
....
|
|
};
|
|
|
|
smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_mem>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
soc {
|
|
....
|
|
qfprom: qfprom@74000 {
|
|
compatible = "qcom,qfprom";
|
|
reg = <0x00074000 0x8ff>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
....
|
|
speedbin_efuse: speedbin@133 {
|
|
reg = <0x133 0x1>;
|
|
bits = <5 3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
Example 2:
|
|
---------
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
CPU0: cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x100>;
|
|
....
|
|
clocks = <&apcs_glb>;
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
power-domains = <&cpr>;
|
|
power-domain-names = "cpr";
|
|
};
|
|
|
|
CPU1: cpu@101 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x101>;
|
|
....
|
|
clocks = <&apcs_glb>;
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
power-domains = <&cpr>;
|
|
power-domain-names = "cpr";
|
|
};
|
|
|
|
CPU2: cpu@102 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x102>;
|
|
....
|
|
clocks = <&apcs_glb>;
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
power-domains = <&cpr>;
|
|
power-domain-names = "cpr";
|
|
};
|
|
|
|
CPU3: cpu@103 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x103>;
|
|
....
|
|
clocks = <&apcs_glb>;
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
power-domains = <&cpr>;
|
|
power-domain-names = "cpr";
|
|
};
|
|
};
|
|
|
|
cpu_opp_table: cpu-opp-table {
|
|
compatible = "operating-points-v2-kryo-cpu";
|
|
opp-shared;
|
|
|
|
opp-1094400000 {
|
|
opp-hz = /bits/ 64 <1094400000>;
|
|
required-opps = <&cpr_opp1>;
|
|
};
|
|
opp-1248000000 {
|
|
opp-hz = /bits/ 64 <1248000000>;
|
|
required-opps = <&cpr_opp2>;
|
|
};
|
|
opp-1401600000 {
|
|
opp-hz = /bits/ 64 <1401600000>;
|
|
required-opps = <&cpr_opp3>;
|
|
};
|
|
};
|
|
|
|
cpr_opp_table: cpr-opp-table {
|
|
compatible = "operating-points-v2-qcom-level";
|
|
|
|
cpr_opp1: opp1 {
|
|
opp-level = <1>;
|
|
qcom,opp-fuse-level = <1>;
|
|
};
|
|
cpr_opp2: opp2 {
|
|
opp-level = <2>;
|
|
qcom,opp-fuse-level = <2>;
|
|
};
|
|
cpr_opp3: opp3 {
|
|
opp-level = <3>;
|
|
qcom,opp-fuse-level = <3>;
|
|
};
|
|
};
|
|
|
|
....
|
|
|
|
soc {
|
|
....
|
|
cpr: power-controller@b018000 {
|
|
compatible = "qcom,qcs404-cpr", "qcom,cpr";
|
|
reg = <0x0b018000 0x1000>;
|
|
....
|
|
vdd-apc-supply = <&pms405_s3>;
|
|
#power-domain-cells = <0>;
|
|
operating-points-v2 = <&cpr_opp_table>;
|
|
....
|
|
};
|
|
};
|