mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 14:43:58 +08:00
e89f443b18
commit fdb487f5c9
("ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it
has some differences with V7")
introduced a fix for checking PJ4 cpuid to not use PJ4 specific
coprocessor access on non-PJ4 platforms.
Unfortunately, this in turn broke Marvell Armada 370/XP, both
comprising Marvell PJ4B CPUs without iWMMXt extension. Instead
of only checking for cpuid, which may not be sufficient to
determine iWMMXt support, the presence of iWMMXt coprocessors
can be checked by enabling and reading the Coprocessor ID
register (wCID, register 0 of CP1).
Therefore this adds an explicit check for the presence and correct
wCID value, before enabling iWMMXt capabilities. As a bonus, also
print the iWMMXt version of a detected coprocessor.
This has been tested to properly detect iWMMXt presence/absence on:
- PJ4, CPUID 0x560f5815, wCID 0x56052001: Marvell Dove, iWMMXt v2
- PJ4B, CPUID 0x561f5811: Marvell Armada 370, no iWMMXt
- PJ4B, CPUID 0x562f5841, wCID 0x56052001: Marvell Armada 1500, iWMMXt v2
- PJ4B, CPUID 0x562f5842: Marvell Armada XP, no iWMMXt
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
134 lines
2.8 KiB
C
134 lines
2.8 KiB
C
/*
|
|
* linux/arch/arm/kernel/pj4-cp0.c
|
|
*
|
|
* PJ4 iWMMXt coprocessor context switching and handling
|
|
*
|
|
* Copyright (c) 2010 Marvell International Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/types.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/signal.h>
|
|
#include <linux/sched.h>
|
|
#include <linux/init.h>
|
|
#include <linux/io.h>
|
|
#include <asm/thread_notify.h>
|
|
#include <asm/cputype.h>
|
|
|
|
static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
|
|
{
|
|
struct thread_info *thread = t;
|
|
|
|
switch (cmd) {
|
|
case THREAD_NOTIFY_FLUSH:
|
|
/*
|
|
* flush_thread() zeroes thread->fpstate, so no need
|
|
* to do anything here.
|
|
*
|
|
* FALLTHROUGH: Ensure we don't try to overwrite our newly
|
|
* initialised state information on the first fault.
|
|
*/
|
|
|
|
case THREAD_NOTIFY_EXIT:
|
|
iwmmxt_task_release(thread);
|
|
break;
|
|
|
|
case THREAD_NOTIFY_SWITCH:
|
|
iwmmxt_task_switch(thread);
|
|
break;
|
|
}
|
|
|
|
return NOTIFY_DONE;
|
|
}
|
|
|
|
static struct notifier_block __maybe_unused iwmmxt_notifier_block = {
|
|
.notifier_call = iwmmxt_do,
|
|
};
|
|
|
|
|
|
static u32 __init pj4_cp_access_read(void)
|
|
{
|
|
u32 value;
|
|
|
|
__asm__ __volatile__ (
|
|
"mrc p15, 0, %0, c1, c0, 2\n\t"
|
|
: "=r" (value));
|
|
return value;
|
|
}
|
|
|
|
static void __init pj4_cp_access_write(u32 value)
|
|
{
|
|
u32 temp;
|
|
|
|
__asm__ __volatile__ (
|
|
"mcr p15, 0, %1, c1, c0, 2\n\t"
|
|
"mrc p15, 0, %0, c1, c0, 2\n\t"
|
|
"mov %0, %0\n\t"
|
|
"sub pc, pc, #4\n\t"
|
|
: "=r" (temp) : "r" (value));
|
|
}
|
|
|
|
static int __init pj4_get_iwmmxt_version(void)
|
|
{
|
|
u32 cp_access, wcid;
|
|
|
|
cp_access = pj4_cp_access_read();
|
|
pj4_cp_access_write(cp_access | 0xf);
|
|
|
|
/* check if coprocessor 0 and 1 are available */
|
|
if ((pj4_cp_access_read() & 0xf) != 0xf) {
|
|
pj4_cp_access_write(cp_access);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* read iWMMXt coprocessor id register p1, c0 */
|
|
__asm__ __volatile__ ("mrc p1, 0, %0, c0, c0, 0\n" : "=r" (wcid));
|
|
|
|
pj4_cp_access_write(cp_access);
|
|
|
|
/* iWMMXt v1 */
|
|
if ((wcid & 0xffffff00) == 0x56051000)
|
|
return 1;
|
|
/* iWMMXt v2 */
|
|
if ((wcid & 0xffffff00) == 0x56052000)
|
|
return 2;
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
|
|
* switch code handle iWMMXt context switching.
|
|
*/
|
|
static int __init pj4_cp0_init(void)
|
|
{
|
|
u32 __maybe_unused cp_access;
|
|
int vers;
|
|
|
|
if (!cpu_is_pj4())
|
|
return 0;
|
|
|
|
vers = pj4_get_iwmmxt_version();
|
|
if (vers < 0)
|
|
return 0;
|
|
|
|
#ifndef CONFIG_IWMMXT
|
|
pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n");
|
|
#else
|
|
cp_access = pj4_cp_access_read() & ~0xf;
|
|
pj4_cp_access_write(cp_access);
|
|
|
|
pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers);
|
|
elf_hwcap |= HWCAP_IWMMXT;
|
|
thread_register_notifier(&iwmmxt_notifier_block);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
late_initcall(pj4_cp0_init);
|