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https://github.com/edk2-porting/linux-next.git
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c0e09200dc
With the coming of kernel based modesetting and the memory manager stuff, the everything in one directory approach was getting very ugly and starting to be unmanageable. This restructures the drm along the lines of other kernel components. It creates a drivers/gpu/drm directory and moves the hw drivers into subdirectores. It moves the includes into an include/drm, and sets up the unifdef for the userspace headers we should be exporting. Signed-off-by: Dave Airlie <airlied@redhat.com>
141 lines
5.3 KiB
C
141 lines
5.3 KiB
C
/* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro
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*
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* Copyright 2005 Thomas Hellstrom.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Thomas Hellstrom.
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* Register info from Digeo Inc.
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*/
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#ifndef _VIA_DMABLIT_H
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#define _VIA_DMABLIT_H
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#include <linux/dma-mapping.h>
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#define VIA_NUM_BLIT_ENGINES 2
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#define VIA_NUM_BLIT_SLOTS 8
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struct _drm_via_descriptor;
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typedef struct _drm_via_sg_info {
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struct page **pages;
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unsigned long num_pages;
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struct _drm_via_descriptor **desc_pages;
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int num_desc_pages;
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int num_desc;
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enum dma_data_direction direction;
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unsigned char *bounce_buffer;
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dma_addr_t chain_start;
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uint32_t free_on_sequence;
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unsigned int descriptors_per_page;
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int aborted;
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enum {
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dr_via_device_mapped,
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dr_via_desc_pages_alloc,
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dr_via_pages_locked,
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dr_via_pages_alloc,
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dr_via_sg_init
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} state;
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} drm_via_sg_info_t;
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typedef struct _drm_via_blitq {
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struct drm_device *dev;
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uint32_t cur_blit_handle;
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uint32_t done_blit_handle;
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unsigned serviced;
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unsigned head;
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unsigned cur;
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unsigned num_free;
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unsigned num_outstanding;
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unsigned long end;
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int aborting;
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int is_active;
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drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS];
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spinlock_t blit_lock;
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wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS];
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wait_queue_head_t busy_queue;
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struct work_struct wq;
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struct timer_list poll_timer;
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} drm_via_blitq_t;
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/*
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* PCI DMA Registers
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* Channels 2 & 3 don't seem to be implemented in hardware.
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*/
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#define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */
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#define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */
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#define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */
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#define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */
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#define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */
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#define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */
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#define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */
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#define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */
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#define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */
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#define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */
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#define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */
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#define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */
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#define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */
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#define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */
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#define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */
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#define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */
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#define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */
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#define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */
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#define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */
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#define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */
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#define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */
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#define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */
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#define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */
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#define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */
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#define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */
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/* Define for DMA engine */
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/* DPR */
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#define VIA_DMA_DPR_EC (1<<1) /* end of chain */
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#define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */
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#define VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */
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/* MR */
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#define VIA_DMA_MR_CM (1<<0) /* chaining mode */
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#define VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */
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#define VIA_DMA_MR_HENDMACMD (1<<7) /* ? */
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/* CSR */
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#define VIA_DMA_CSR_DE (1<<0) /* DMA enable */
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#define VIA_DMA_CSR_TS (1<<1) /* transfer start */
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#define VIA_DMA_CSR_TA (1<<2) /* transfer abort */
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#define VIA_DMA_CSR_TD (1<<3) /* transfer done */
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#define VIA_DMA_CSR_DD (1<<4) /* descriptor done */
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#define VIA_DMA_DPR_EC (1<<1) /* end of chain */
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#endif
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