mirror of
https://github.com/edk2-porting/linux-next.git
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b6195aab9c
And update to the actual product naming as the press release is now out. http://newsroom.intel.com/docs/DOC-2553#pressmaterials - Fixes the wrong ifdef check - Fixes the missing crtc count declaration Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
352 lines
8.7 KiB
C
352 lines
8.7 KiB
C
/**************************************************************************
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* Copyright (c) 2011, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#include <linux/backlight.h>
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#include <drm/drmP.h>
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#include <drm/drm.h>
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#include "gma_drm.h"
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#include "psb_drv.h"
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#include "psb_reg.h"
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#include "psb_intel_reg.h"
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#include "intel_bios.h"
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#include "cdv_device.h"
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#define VGA_SR_INDEX 0x3c4
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#define VGA_SR_DATA 0x3c5
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static void cdv_disable_vga(struct drm_device *dev)
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{
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u8 sr1;
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u32 vga_reg;
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vga_reg = VGACNTRL;
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outb(1, VGA_SR_INDEX);
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sr1 = inb(VGA_SR_DATA);
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outb(sr1 | 1<<5, VGA_SR_DATA);
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udelay(300);
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REG_WRITE(vga_reg, VGA_DISP_DISABLE);
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REG_READ(vga_reg);
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}
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static int cdv_output_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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cdv_disable_vga(dev);
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cdv_intel_crt_init(dev, &dev_priv->mode_dev);
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cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
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/* These bits indicate HDMI not SDVO on CDV, but we don't yet support
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the HDMI interface */
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if (REG_READ(SDVOB) & SDVO_DETECTED)
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cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
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if (REG_READ(SDVOC) & SDVO_DETECTED)
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cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
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return 0;
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}
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#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
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/*
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* Poulsbo Backlight Interfaces
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*/
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#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
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#define BLC_PWM_FREQ_CALC_CONSTANT 32
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#define MHz 1000000
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#define PSB_BLC_PWM_PRECISION_FACTOR 10
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#define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
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#define PSB_BLC_MIN_PWM_REG_FREQ 0x2
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#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
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#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
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static int cdv_brightness;
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static struct backlight_device *cdv_backlight_device;
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static int cdv_get_brightness(struct backlight_device *bd)
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{
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/* return locally cached var instead of HW read (due to DPST etc.) */
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/* FIXME: ideally return actual value in case firmware fiddled with
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it */
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return cdv_brightness;
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}
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static int cdv_backlight_setup(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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unsigned long core_clock;
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/* u32 bl_max_freq; */
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/* unsigned long value; */
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u16 bl_max_freq;
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uint32_t value;
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uint32_t blc_pwm_precision_factor;
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/* get bl_max_freq and pol from dev_priv*/
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if (!dev_priv->lvds_bl) {
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dev_err(dev->dev, "Has no valid LVDS backlight info\n");
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return -ENOENT;
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}
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bl_max_freq = dev_priv->lvds_bl->freq;
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blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
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core_clock = dev_priv->core_freq;
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value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
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value *= blc_pwm_precision_factor;
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value /= bl_max_freq;
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value /= blc_pwm_precision_factor;
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if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
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value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
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return -ERANGE;
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else {
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/* FIXME */
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}
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return 0;
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}
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static int cdv_set_brightness(struct backlight_device *bd)
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{
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int level = bd->props.brightness;
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/* Percentage 1-100% being valid */
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if (level < 1)
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level = 1;
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/*cdv_intel_lvds_set_brightness(dev, level); FIXME */
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cdv_brightness = level;
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return 0;
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}
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static const struct backlight_ops cdv_ops = {
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.get_brightness = cdv_get_brightness,
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.update_status = cdv_set_brightness,
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};
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static int cdv_backlight_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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int ret;
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struct backlight_properties props;
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memset(&props, 0, sizeof(struct backlight_properties));
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props.max_brightness = 100;
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props.type = BACKLIGHT_PLATFORM;
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cdv_backlight_device = backlight_device_register("psb-bl",
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NULL, (void *)dev, &cdv_ops, &props);
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if (IS_ERR(cdv_backlight_device))
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return PTR_ERR(cdv_backlight_device);
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ret = cdv_backlight_setup(dev);
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if (ret < 0) {
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backlight_device_unregister(cdv_backlight_device);
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cdv_backlight_device = NULL;
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return ret;
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}
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cdv_backlight_device->props.brightness = 100;
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cdv_backlight_device->props.max_brightness = 100;
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backlight_update_status(cdv_backlight_device);
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dev_priv->backlight_device = cdv_backlight_device;
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return 0;
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}
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#endif
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/*
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* Provide the Cedarview specific chip logic and low level methods
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* for power management
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*
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* FIXME: we need to implement the apm/ospm base management bits
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* for this and the MID devices.
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*/
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static inline u32 CDV_MSG_READ32(uint port, uint offset)
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{
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int mcr = (0x10<<24) | (port << 16) | (offset << 8);
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uint32_t ret_val = 0;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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pci_write_config_dword(pci_root, 0xD0, mcr);
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pci_read_config_dword(pci_root, 0xD4, &ret_val);
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pci_dev_put(pci_root);
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return ret_val;
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}
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static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
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{
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int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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pci_write_config_dword(pci_root, 0xD4, value);
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pci_write_config_dword(pci_root, 0xD0, mcr);
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pci_dev_put(pci_root);
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}
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#define PSB_APM_CMD 0x0
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#define PSB_APM_STS 0x04
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#define PSB_PM_SSC 0x20
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#define PSB_PM_SSS 0x30
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#define PSB_PWRGT_GFX_MASK 0x3
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#define CDV_PWRGT_DISPLAY_CNTR 0x000fc00c
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#define CDV_PWRGT_DISPLAY_STS 0x000fc00c
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static void cdv_init_pm(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 pwr_cnt;
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int i;
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dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
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PSB_APMBA) & 0xFFFF;
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dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
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PSB_OSPMBA) & 0xFFFF;
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/* Force power on for now */
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pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
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pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
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outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
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for (i = 0; i < 5; i++) {
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u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
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if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
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break;
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udelay(10);
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}
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pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
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pwr_cnt &= ~CDV_PWRGT_DISPLAY_CNTR;
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outl(pwr_cnt, dev_priv->ospm_base + PSB_PM_SSC);
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for (i = 0; i < 5; i++) {
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u32 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
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if ((pwr_sts & CDV_PWRGT_DISPLAY_STS) == 0)
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break;
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udelay(10);
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}
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}
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/**
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* cdv_save_display_registers - save registers lost on suspend
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* @dev: our DRM device
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*
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* Save the state we need in order to be able to restore the interface
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* upon resume from suspend
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*
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* FIXME: review
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*/
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static int cdv_save_display_registers(struct drm_device *dev)
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{
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return 0;
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}
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/**
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* cdv_restore_display_registers - restore lost register state
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* @dev: our DRM device
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*
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* Restore register state that was lost during suspend and resume.
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*
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* FIXME: review
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*/
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static int cdv_restore_display_registers(struct drm_device *dev)
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{
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return 0;
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}
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static int cdv_power_down(struct drm_device *dev)
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{
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return 0;
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}
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static int cdv_power_up(struct drm_device *dev)
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{
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return 0;
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}
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/* FIXME ? - shared with Poulsbo */
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static void cdv_get_core_freq(struct drm_device *dev)
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{
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uint32_t clock;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct drm_psb_private *dev_priv = dev->dev_private;
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pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
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pci_read_config_dword(pci_root, 0xD4, &clock);
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pci_dev_put(pci_root);
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switch (clock & 0x07) {
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case 0:
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dev_priv->core_freq = 100;
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break;
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case 1:
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dev_priv->core_freq = 133;
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break;
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case 2:
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dev_priv->core_freq = 150;
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break;
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case 3:
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dev_priv->core_freq = 178;
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break;
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case 4:
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dev_priv->core_freq = 200;
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break;
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case 5:
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case 6:
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case 7:
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dev_priv->core_freq = 266;
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default:
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dev_priv->core_freq = 0;
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}
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}
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static int cdv_chip_setup(struct drm_device *dev)
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{
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cdv_get_core_freq(dev);
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gma_intel_opregion_init(dev);
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psb_intel_init_bios(dev);
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return 0;
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}
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/* CDV is much like Poulsbo but has MID like SGX offsets and PM */
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const struct psb_ops cdv_chip_ops = {
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.name = "GMA3600/3650",
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.accel_2d = 0,
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.pipes = 2,
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.crtcs = 2,
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.sgx_offset = MRST_SGX_OFFSET,
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.chip_setup = cdv_chip_setup,
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.crtc_helper = &cdv_intel_helper_funcs,
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.crtc_funcs = &cdv_intel_crtc_funcs,
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.output_init = cdv_output_init,
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#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
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.backlight_init = cdv_backlight_init,
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#endif
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.init_pm = cdv_init_pm,
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.save_regs = cdv_save_display_registers,
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.restore_regs = cdv_restore_display_registers,
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.power_down = cdv_power_down,
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.power_up = cdv_power_up,
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};
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