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Add the AppliedMicro X-Gene SOC PCIe host controller driver. The X-Gene PCIe controller supports up to 8 lanes and GEN3 speed. The X-Gene SOC supports up to 5 PCIe ports. [bhelgaas: folded in MAINTAINERS and bindings updates] Tested-by: Ming Lei <ming.lei@canonical.com> Tested-by: Dann Frazier <dann.frazier@canonical.com> Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> (driver)
58 lines
1.9 KiB
Plaintext
58 lines
1.9 KiB
Plaintext
* AppliedMicro X-Gene PCIe interface
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Required properties:
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- device_type: set to "pci"
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- compatible: should contain "apm,xgene-pcie" to identify the core.
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names
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property.
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- reg-names: Must include the following entries:
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"csr": controller configuration registers.
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"cfg": pcie configuration space registers.
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- ranges: ranges for the outbound memory, I/O regions.
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- dma-ranges: ranges for the inbound memory regions.
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map: standard PCI properties
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to define the mapping of the PCIe interface to interrupt
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numbers.
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- clocks: from common clock binding: handle to pci clock.
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Optional properties:
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- status: Either "ok" or "disabled".
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- dma-coherent: Present if dma operations are coherent
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Example:
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SoC specific DT Entry:
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pcie0: pcie@1f2b0000 {
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status = "disabled";
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device_type = "pci";
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compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
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0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
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reg-names = "csr", "cfg";
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ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
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0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
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dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
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0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
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0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
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0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
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0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
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dma-coherent;
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clocks = <&pcie0clk 0>;
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};
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Board specific DT Entry:
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&pcie0 {
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status = "ok";
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};
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