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bd7d95cafb
When we emulate a guest instruction, we don't advance the hardware singlestep state machine, and thus the guest will receive a software step exception after a next instruction which is not emulated by the host. We bodge around this in an ad-hoc fashion. Sometimes we explicitly check whether userspace requested a single step, and fake a debug exception from within the kernel. Other times, we advance the HW singlestep state rely on the HW to generate the exception for us. Thus, the observed step behaviour differs for host and guest. Let's make this simpler and consistent by always advancing the HW singlestep state machine when we skip an instruction. Thus we can rely on the hardware to generate the singlestep exception for us, and never need to explicitly check for an active-pending step, nor do we need to fake a debug exception from the guest. Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
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* Copyright (C) 2012-2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/compiler.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/kvm_host.h>
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#include <linux/swab.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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static bool __hyp_text __is_be(struct kvm_vcpu *vcpu)
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{
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if (vcpu_mode_is_32bit(vcpu))
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return !!(read_sysreg_el2(spsr) & PSR_AA32_E_BIT);
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return !!(read_sysreg(SCTLR_EL1) & SCTLR_ELx_EE);
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}
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/*
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* __vgic_v2_perform_cpuif_access -- perform a GICV access on behalf of the
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* guest.
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*
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* @vcpu: the offending vcpu
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*
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* Returns:
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* 1: GICV access successfully performed
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* 0: Not a GICV access
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* -1: Illegal GICV access successfully performed
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*/
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int __hyp_text __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = kern_hyp_va(vcpu->kvm);
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struct vgic_dist *vgic = &kvm->arch.vgic;
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phys_addr_t fault_ipa;
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void __iomem *addr;
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int rd;
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/* Build the full address */
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fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);
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fault_ipa |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
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/* If not for GICV, move on */
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if (fault_ipa < vgic->vgic_cpu_base ||
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fault_ipa >= (vgic->vgic_cpu_base + KVM_VGIC_V2_CPU_SIZE))
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return 0;
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/* Reject anything but a 32bit access */
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if (kvm_vcpu_dabt_get_as(vcpu) != sizeof(u32)) {
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__kvm_skip_instr(vcpu);
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return -1;
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}
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/* Not aligned? Don't bother */
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if (fault_ipa & 3) {
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__kvm_skip_instr(vcpu);
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return -1;
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}
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rd = kvm_vcpu_dabt_get_rd(vcpu);
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addr = hyp_symbol_addr(kvm_vgic_global_state)->vcpu_hyp_va;
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addr += fault_ipa - vgic->vgic_cpu_base;
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if (kvm_vcpu_dabt_iswrite(vcpu)) {
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u32 data = vcpu_get_reg(vcpu, rd);
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if (__is_be(vcpu)) {
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/* guest pre-swabbed data, undo this for writel() */
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data = swab32(data);
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}
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writel_relaxed(data, addr);
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} else {
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u32 data = readl_relaxed(addr);
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if (__is_be(vcpu)) {
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/* guest expects swabbed data */
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data = swab32(data);
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}
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vcpu_set_reg(vcpu, rd, data);
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}
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__kvm_skip_instr(vcpu);
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return 1;
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}
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