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d7c9661115
This chip is no longer being actively developed for (it was superceded by the TILEPro64 in 2008), and in any case the existing compiler and toolchain in the community do not support it. It's unlikely that the kernel works with TILE64 at this point as the configuration has not been tested in years. The support is also awkward as it requires maintaining a significant number of ifdefs. So, just remove it altogether. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
145 lines
4.1 KiB
C
145 lines
4.1 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_BARRIER_H
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#define _ASM_TILE_BARRIER_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <arch/chip.h>
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#include <arch/spr_def.h>
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#include <asm/timex.h>
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/*
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like this where there are no data dependencies.
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*/
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#define read_barrier_depends() do { } while (0)
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#define __sync() __insn_mf()
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#include <hv/syscall_public.h>
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/*
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* Issue an uncacheable load to each memory controller, then
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* wait until those loads have completed.
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*/
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static inline void __mb_incoherent(void)
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{
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long clobber_r10;
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asm volatile("swint2"
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: "=R10" (clobber_r10)
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: "R10" (HV_SYS_fence_incoherent)
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: "r0", "r1", "r2", "r3", "r4",
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"r5", "r6", "r7", "r8", "r9",
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"r11", "r12", "r13", "r14",
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"r15", "r16", "r17", "r18", "r19",
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"r20", "r21", "r22", "r23", "r24",
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"r25", "r26", "r27", "r28", "r29");
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}
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/* Fence to guarantee visibility of stores to incoherent memory. */
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static inline void
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mb_incoherent(void)
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{
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__insn_mf();
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{
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#if CHIP_HAS_TILE_WRITE_PENDING()
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const unsigned long WRITE_TIMEOUT_CYCLES = 400;
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unsigned long start = get_cycles_low();
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do {
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if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
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return;
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} while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
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#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
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(void) __mb_incoherent();
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}
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}
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#define fast_wmb() __sync()
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#define fast_rmb() __sync()
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#define fast_mb() __sync()
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#define fast_iob() mb_incoherent()
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#define wmb() fast_wmb()
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#define rmb() fast_rmb()
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#define mb() fast_mb()
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#define iob() fast_iob()
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while (0)
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#endif
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#define set_mb(var, value) \
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do { var = value; mb(); } while (0)
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_TILE_BARRIER_H */
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