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306e440daf
Introduce proper declarations for i8253_lock and i8259A_lock. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
260 lines
6.9 KiB
C
260 lines
6.9 KiB
C
/* Cyclone-timer:
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* This code implements timer_ops for the cyclone counter found
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* on IBM x440, x360, and other Summit based systems.
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*
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* Copyright (C) 2002 IBM, John Stultz (johnstul@us.ibm.com)
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*/
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/jiffies.h>
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#include <asm/timer.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/fixmap.h>
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#include <asm/i8253.h>
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#include "io_ports.h"
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/* Number of usecs that the last interrupt was delayed */
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static int delay_at_last_interrupt;
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#define CYCLONE_CBAR_ADDR 0xFEB00CD0
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#define CYCLONE_PMCC_OFFSET 0x51A0
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#define CYCLONE_MPMC_OFFSET 0x51D0
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#define CYCLONE_MPCS_OFFSET 0x51A8
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#define CYCLONE_TIMER_FREQ 100000000
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#define CYCLONE_TIMER_MASK (((u64)1<<40)-1) /* 40 bit mask */
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int use_cyclone = 0;
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static u32* volatile cyclone_timer; /* Cyclone MPMC0 register */
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static u32 last_cyclone_low;
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static u32 last_cyclone_high;
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static unsigned long long monotonic_base;
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static seqlock_t monotonic_lock = SEQLOCK_UNLOCKED;
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/* helper macro to atomically read both cyclone counter registers */
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#define read_cyclone_counter(low,high) \
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do{ \
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high = cyclone_timer[1]; low = cyclone_timer[0]; \
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} while (high != cyclone_timer[1]);
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static void mark_offset_cyclone(void)
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{
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unsigned long lost, delay;
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unsigned long delta = last_cyclone_low;
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int count;
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unsigned long long this_offset, last_offset;
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write_seqlock(&monotonic_lock);
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last_offset = ((unsigned long long)last_cyclone_high<<32)|last_cyclone_low;
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spin_lock(&i8253_lock);
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read_cyclone_counter(last_cyclone_low,last_cyclone_high);
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/* read values for delay_at_last_interrupt */
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outb_p(0x00, 0x43); /* latch the count ASAP */
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count = inb_p(0x40); /* read the latched count */
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count |= inb(0x40) << 8;
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/*
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* VIA686a test code... reset the latch if count > max + 1
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* from timer_pit.c - cjb
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*/
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if (count > LATCH) {
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outb_p(0x34, PIT_MODE);
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outb_p(LATCH & 0xff, PIT_CH0);
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outb(LATCH >> 8, PIT_CH0);
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count = LATCH - 1;
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}
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spin_unlock(&i8253_lock);
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/* lost tick compensation */
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delta = last_cyclone_low - delta;
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delta /= (CYCLONE_TIMER_FREQ/1000000);
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delta += delay_at_last_interrupt;
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lost = delta/(1000000/HZ);
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delay = delta%(1000000/HZ);
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if (lost >= 2)
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jiffies_64 += lost-1;
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/* update the monotonic base value */
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this_offset = ((unsigned long long)last_cyclone_high<<32)|last_cyclone_low;
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monotonic_base += (this_offset - last_offset) & CYCLONE_TIMER_MASK;
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write_sequnlock(&monotonic_lock);
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/* calculate delay_at_last_interrupt */
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count = ((LATCH-1) - count) * TICK_SIZE;
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delay_at_last_interrupt = (count + LATCH/2) / LATCH;
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/* catch corner case where tick rollover occured
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* between cyclone and pit reads (as noted when
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* usec delta is > 90% # of usecs/tick)
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*/
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if (lost && abs(delay - delay_at_last_interrupt) > (900000/HZ))
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jiffies_64++;
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}
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static unsigned long get_offset_cyclone(void)
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{
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u32 offset;
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if(!cyclone_timer)
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return delay_at_last_interrupt;
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/* Read the cyclone timer */
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offset = cyclone_timer[0];
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/* .. relative to previous jiffy */
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offset = offset - last_cyclone_low;
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/* convert cyclone ticks to microseconds */
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/* XXX slow, can we speed this up? */
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offset = offset/(CYCLONE_TIMER_FREQ/1000000);
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/* our adjusted time offset in microseconds */
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return delay_at_last_interrupt + offset;
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}
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static unsigned long long monotonic_clock_cyclone(void)
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{
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u32 now_low, now_high;
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unsigned long long last_offset, this_offset, base;
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unsigned long long ret;
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unsigned seq;
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/* atomically read monotonic base & last_offset */
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do {
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seq = read_seqbegin(&monotonic_lock);
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last_offset = ((unsigned long long)last_cyclone_high<<32)|last_cyclone_low;
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base = monotonic_base;
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} while (read_seqretry(&monotonic_lock, seq));
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/* Read the cyclone counter */
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read_cyclone_counter(now_low,now_high);
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this_offset = ((unsigned long long)now_high<<32)|now_low;
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/* convert to nanoseconds */
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ret = base + ((this_offset - last_offset)&CYCLONE_TIMER_MASK);
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return ret * (1000000000 / CYCLONE_TIMER_FREQ);
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}
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static int __init init_cyclone(char* override)
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{
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u32* reg;
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u32 base; /* saved cyclone base address */
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u32 pageaddr; /* page that contains cyclone_timer register */
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u32 offset; /* offset from pageaddr to cyclone_timer register */
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int i;
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/* check clock override */
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if (override[0] && strncmp(override,"cyclone",7))
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return -ENODEV;
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/*make sure we're on a summit box*/
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if(!use_cyclone) return -ENODEV;
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printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
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/* find base address */
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pageaddr = (CYCLONE_CBAR_ADDR)&PAGE_MASK;
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offset = (CYCLONE_CBAR_ADDR)&(~PAGE_MASK);
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set_fixmap_nocache(FIX_CYCLONE_TIMER, pageaddr);
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reg = (u32*)(fix_to_virt(FIX_CYCLONE_TIMER) + offset);
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if(!reg){
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printk(KERN_ERR "Summit chipset: Could not find valid CBAR register.\n");
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return -ENODEV;
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}
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base = *reg;
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if(!base){
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printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
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return -ENODEV;
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}
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/* setup PMCC */
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pageaddr = (base + CYCLONE_PMCC_OFFSET)&PAGE_MASK;
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offset = (base + CYCLONE_PMCC_OFFSET)&(~PAGE_MASK);
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set_fixmap_nocache(FIX_CYCLONE_TIMER, pageaddr);
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reg = (u32*)(fix_to_virt(FIX_CYCLONE_TIMER) + offset);
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if(!reg){
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printk(KERN_ERR "Summit chipset: Could not find valid PMCC register.\n");
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return -ENODEV;
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}
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reg[0] = 0x00000001;
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/* setup MPCS */
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pageaddr = (base + CYCLONE_MPCS_OFFSET)&PAGE_MASK;
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offset = (base + CYCLONE_MPCS_OFFSET)&(~PAGE_MASK);
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set_fixmap_nocache(FIX_CYCLONE_TIMER, pageaddr);
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reg = (u32*)(fix_to_virt(FIX_CYCLONE_TIMER) + offset);
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if(!reg){
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printk(KERN_ERR "Summit chipset: Could not find valid MPCS register.\n");
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return -ENODEV;
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}
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reg[0] = 0x00000001;
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/* map in cyclone_timer */
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pageaddr = (base + CYCLONE_MPMC_OFFSET)&PAGE_MASK;
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offset = (base + CYCLONE_MPMC_OFFSET)&(~PAGE_MASK);
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set_fixmap_nocache(FIX_CYCLONE_TIMER, pageaddr);
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cyclone_timer = (u32*)(fix_to_virt(FIX_CYCLONE_TIMER) + offset);
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if(!cyclone_timer){
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printk(KERN_ERR "Summit chipset: Could not find valid MPMC register.\n");
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return -ENODEV;
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}
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/*quick test to make sure its ticking*/
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for(i=0; i<3; i++){
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u32 old = cyclone_timer[0];
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int stall = 100;
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while(stall--) barrier();
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if(cyclone_timer[0] == old){
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printk(KERN_ERR "Summit chipset: Counter not counting! DISABLED\n");
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cyclone_timer = 0;
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return -ENODEV;
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}
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}
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init_cpu_khz();
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/* Everything looks good! */
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return 0;
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}
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static void delay_cyclone(unsigned long loops)
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{
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unsigned long bclock, now;
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if(!cyclone_timer)
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return;
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bclock = cyclone_timer[0];
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do {
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rep_nop();
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now = cyclone_timer[0];
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} while ((now-bclock) < loops);
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}
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/************************************************************/
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/* cyclone timer_opts struct */
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static struct timer_opts timer_cyclone = {
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.name = "cyclone",
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.mark_offset = mark_offset_cyclone,
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.get_offset = get_offset_cyclone,
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.monotonic_clock = monotonic_clock_cyclone,
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.delay = delay_cyclone,
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};
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struct init_timer_opts __initdata timer_cyclone_init = {
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.init = init_cyclone,
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.opts = &timer_cyclone,
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};
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