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d9cdeb814f
Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check the same before restoring the cache in resume. This is needed for single kernel image. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
90 lines
2.4 KiB
ArmAsm
90 lines
2.4 KiB
ArmAsm
/*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Common S5P Sleep Code
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* Based on S3C64XX sleep code by:
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* Ben Dooks, (c) 2008 Simtec Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/hardware/cache-l2x0.h>
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#define CPU_MASK 0xff0ffff0
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#define CPU_CORTEX_A9 0x410fc090
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/*
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* The following code is located into the .data section. This is to
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* allow l2x0_regs_phys to be accessed with a relative load while we
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* can't rely on any MMU translation. We could have put l2x0_regs_phys
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* in the .text section as well, but some setups might insist on it to
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* be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
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*/
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.data
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.align
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/*
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* sleep magic, to allow the bootloader to check for an valid
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* image to resume to. Must be the first word before the
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* s3c_cpu_resume entry.
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*/
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.word 0x2bedf00d
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/*
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* s3c_cpu_resume
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*
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* resume code entry for bootloader to call
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*/
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ENTRY(s3c_cpu_resume)
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#ifdef CONFIG_CACHE_L2X0
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mrc p15, 0, r0, c0, c0, 0
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ldr r1, =CPU_MASK
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and r0, r0, r1
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ldr r1, =CPU_CORTEX_A9
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cmp r0, r1
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bne resume_l2on
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adr r0, l2x0_regs_phys
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ldr r0, [r0]
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ldr r1, [r0, #L2X0_R_PHY_BASE]
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ldr r2, [r1, #L2X0_CTRL]
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tst r2, #0x1
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bne resume_l2on
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ldr r2, [r0, #L2X0_R_AUX_CTRL]
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str r2, [r1, #L2X0_AUX_CTRL]
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ldr r2, [r0, #L2X0_R_TAG_LATENCY]
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str r2, [r1, #L2X0_TAG_LATENCY_CTRL]
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ldr r2, [r0, #L2X0_R_DATA_LATENCY]
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str r2, [r1, #L2X0_DATA_LATENCY_CTRL]
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ldr r2, [r0, #L2X0_R_PREFETCH_CTRL]
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str r2, [r1, #L2X0_PREFETCH_CTRL]
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ldr r2, [r0, #L2X0_R_PWR_CTRL]
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str r2, [r1, #L2X0_POWER_CTRL]
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mov r2, #1
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str r2, [r1, #L2X0_CTRL]
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resume_l2on:
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#endif
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b cpu_resume
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ENDPROC(s3c_cpu_resume)
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#ifdef CONFIG_CACHE_L2X0
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.globl l2x0_regs_phys
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l2x0_regs_phys:
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.long 0
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#endif
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