mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-28 15:13:55 +08:00
a6e03dd451
The mvmdio driver accesses some register of the Ethernet unit. It therefore takes a reference and enables a clock. However, on Armada 370/XP, no clock specification was given in the Device Tree, which leads the mvmdio driver to fail when being used as a module and loaded before the mvneta driver: it tries to access a register from a hardware unit that isn't clocked. Cc: stable@vger.kernel.org Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1395790439-21332-2-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
286 lines
6.3 KiB
Plaintext
286 lines
6.3 KiB
Plaintext
/*
|
|
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
|
|
*
|
|
* Copyright (C) 2012 Marvell
|
|
*
|
|
* Lior Amsalem <alior@marvell.com>
|
|
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
|
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
* Ben Dooks <ben.dooks@codethink.co.uk>
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*
|
|
* This file contains the definitions that are common to the Armada
|
|
* 370 and Armada XP SoC.
|
|
*/
|
|
|
|
/include/ "skeleton64.dtsi"
|
|
|
|
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
|
|
|
/ {
|
|
model = "Marvell Armada 370 and XP SoC";
|
|
compatible = "marvell,armada-370-xp";
|
|
|
|
aliases {
|
|
eth0 = ð0;
|
|
eth1 = ð1;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cpu@0 {
|
|
compatible = "marvell,sheeva-v7";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
controller = <&mbusc>;
|
|
interrupt-parent = <&mpic>;
|
|
pcie-mem-aperture = <0xf8000000 0x7e00000>;
|
|
pcie-io-aperture = <0xffe00000 0x100000>;
|
|
|
|
devbus-bootcs {
|
|
compatible = "marvell,mvebu-devbus";
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
|
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
devbus-cs0 {
|
|
compatible = "marvell,mvebu-devbus";
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
|
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
devbus-cs1 {
|
|
compatible = "marvell,mvebu-devbus";
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
|
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
devbus-cs2 {
|
|
compatible = "marvell,mvebu-devbus";
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
|
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
devbus-cs3 {
|
|
compatible = "marvell,mvebu-devbus";
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
|
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
internal-regs {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
|
|
|
rtc@10300 {
|
|
compatible = "marvell,orion-rtc";
|
|
reg = <0x10300 0x20>;
|
|
interrupts = <50>;
|
|
};
|
|
|
|
spi0: spi@10600 {
|
|
compatible = "marvell,orion-spi";
|
|
reg = <0x10600 0x28>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
interrupts = <30>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@10680 {
|
|
compatible = "marvell,orion-spi";
|
|
reg = <0x10680 0x28>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <1>;
|
|
interrupts = <92>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@11000 {
|
|
compatible = "marvell,mv64xxx-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <31>;
|
|
timeout-ms = <1000>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@11100 {
|
|
compatible = "marvell,mv64xxx-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <32>;
|
|
timeout-ms = <1000>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
serial@12000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x12000 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <41>;
|
|
reg-io-width = <1>;
|
|
status = "disabled";
|
|
};
|
|
serial@12100 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x12100 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <42>;
|
|
reg-io-width = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
coredivclk: corediv-clock@18740 {
|
|
compatible = "marvell,armada-370-corediv-clock";
|
|
reg = <0x18740 0xc>;
|
|
#clock-cells = <1>;
|
|
clocks = <&mainpll>;
|
|
clock-output-names = "nand";
|
|
};
|
|
|
|
mbusc: mbus-controller@20000 {
|
|
compatible = "marvell,mbus-controller";
|
|
reg = <0x20000 0x100>, <0x20180 0x20>;
|
|
};
|
|
|
|
mpic: interrupt-controller@20000 {
|
|
compatible = "marvell,mpic";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-controller;
|
|
msi-controller;
|
|
};
|
|
|
|
coherency-fabric@20200 {
|
|
compatible = "marvell,coherency-fabric";
|
|
reg = <0x20200 0xb0>, <0x21010 0x1c>;
|
|
};
|
|
|
|
timer@20300 {
|
|
reg = <0x20300 0x30>, <0x21040 0x30>;
|
|
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
|
|
};
|
|
|
|
watchdog@20300 {
|
|
reg = <0x20300 0x34>, <0x20704 0x4>;
|
|
};
|
|
|
|
usb@50000 {
|
|
compatible = "marvell,orion-ehci";
|
|
reg = <0x50000 0x500>;
|
|
interrupts = <45>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@51000 {
|
|
compatible = "marvell,orion-ehci";
|
|
reg = <0x51000 0x500>;
|
|
interrupts = <46>;
|
|
status = "disabled";
|
|
};
|
|
|
|
eth0: ethernet@70000 {
|
|
compatible = "marvell,armada-370-neta";
|
|
reg = <0x70000 0x4000>;
|
|
interrupts = <8>;
|
|
clocks = <&gateclk 4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "marvell,orion-mdio";
|
|
reg = <0x72004 0x4>;
|
|
clocks = <&gateclk 4>;
|
|
};
|
|
|
|
eth1: ethernet@74000 {
|
|
compatible = "marvell,armada-370-neta";
|
|
reg = <0x74000 0x4000>;
|
|
interrupts = <10>;
|
|
clocks = <&gateclk 3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata@a0000 {
|
|
compatible = "marvell,armada-370-sata";
|
|
reg = <0xa0000 0x5000>;
|
|
interrupts = <55>;
|
|
clocks = <&gateclk 15>, <&gateclk 30>;
|
|
clock-names = "0", "1";
|
|
status = "disabled";
|
|
};
|
|
|
|
nand@d0000 {
|
|
compatible = "marvell,armada370-nand";
|
|
reg = <0xd0000 0x54>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupts = <113>;
|
|
clocks = <&coredivclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mvsdio@d4000 {
|
|
compatible = "marvell,orion-sdio";
|
|
reg = <0xd4000 0x200>;
|
|
interrupts = <54>;
|
|
clocks = <&gateclk 17>;
|
|
bus-width = <4>;
|
|
cap-sdio-irq;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
/* 2 GHz fixed main PLL */
|
|
mainpll: mainpll {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <2000000000>;
|
|
};
|
|
};
|
|
};
|