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0ea04c7322
Add a description of the External Interrupt Unit (EXIU) interrupt controller as found on the Socionext SynQuacer SoC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
33 lines
1.1 KiB
Plaintext
33 lines
1.1 KiB
Plaintext
Socionext SynQuacer External Interrupt Unit (EXIU)
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The Socionext Synquacer SoC has an external interrupt unit (EXIU)
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that forwards a block of 32 configurable input lines to 32 adjacent
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level-high type GICv3 SPIs.
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Required properties:
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- compatible : Should be "socionext,synquacer-exiu".
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- reg : Specifies base physical address and size of the
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control registers.
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- interrupt-controller : Identifies the node as an interrupt controller.
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value must be 3.
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- interrupt-parent : phandle of the GIC these interrupts are routed to.
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- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
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ones the EXIU forwards its interrups to.
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Notes:
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- Only SPIs can use the EXIU as an interrupt parent.
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Example:
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exiu: interrupt-controller@510c0000 {
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compatible = "socionext,synquacer-exiu";
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reg = <0x0 0x510c0000 0x0 0x20>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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socionext,spi-base = <112>;
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};
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