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c6f0b878f9
On imx35pdk there are two DRAM chip selects that are used: CS0 at 0x80000000 CS1 at 0x90000000 Each bank is connected to 128MB of DRAM, giving a total of 256MB of system DRAM. Fix the memory layout to describe the hardware appropriately. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
69 lines
1.5 KiB
Plaintext
69 lines
1.5 KiB
Plaintext
/*
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* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx35.dtsi"
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/ {
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model = "Freescale i.MX35 Product Development Kit";
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compatible = "fsl,imx35-pdk", "fsl,imx35";
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memory {
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reg = <0x80000000 0x8000000>,
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<0x90000000 0x8000000>;
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};
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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status = "okay";
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};
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&iomuxc {
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imx35-pdk {
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
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MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
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MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
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MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
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MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
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MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
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MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
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MX35_PAD_CTS1__UART1_CTS 0x1c5
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MX35_PAD_RTS1__UART1_RTS 0x1c5
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>;
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};
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};
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};
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&nfc {
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nand-bus-width = <16>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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