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070bd7e491
To make it consistent with the other i.mx SoCs, let's add the cpus nodes. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
139 lines
3.1 KiB
Plaintext
139 lines
3.1 KiB
Plaintext
/*
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* Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "skeleton.dtsi"
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/ {
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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};
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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compatible = "arm,arm1136";
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device_type = "cpu";
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};
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};
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avic: avic-interrupt-controller@60000000 {
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compatible = "fsl,imx31-avic", "fsl,avic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x60000000 0x100000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&avic>;
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ranges;
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aips@43f00000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x43f00000 0x100000>;
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ranges;
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uart1: serial@43f90000 {
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compatible = "fsl,imx31-uart", "fsl,imx21-uart";
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reg = <0x43f90000 0x4000>;
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interrupts = <45>;
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clocks = <&clks 10>, <&clks 30>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart2: serial@43f94000 {
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compatible = "fsl,imx31-uart", "fsl,imx21-uart";
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reg = <0x43f94000 0x4000>;
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interrupts = <32>;
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clocks = <&clks 10>, <&clks 31>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart4: serial@43fb0000 {
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compatible = "fsl,imx31-uart", "fsl,imx21-uart";
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reg = <0x43fb0000 0x4000>;
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clocks = <&clks 10>, <&clks 49>;
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clock-names = "ipg", "per";
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interrupts = <46>;
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status = "disabled";
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};
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uart5: serial@43fb4000 {
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compatible = "fsl,imx31-uart", "fsl,imx21-uart";
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reg = <0x43fb4000 0x4000>;
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interrupts = <47>;
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clocks = <&clks 10>, <&clks 50>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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};
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spba@50000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x100000>;
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ranges;
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uart3: serial@5000c000 {
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compatible = "fsl,imx31-uart", "fsl,imx21-uart";
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reg = <0x5000c000 0x4000>;
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interrupts = <18>;
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clocks = <&clks 10>, <&clks 48>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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iim: iim@5001c000 {
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compatible = "fsl,imx31-iim", "fsl,imx27-iim";
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reg = <0x5001c000 0x1000>;
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interrupts = <19>;
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clocks = <&clks 25>;
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};
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clks: ccm@53f80000{
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compatible = "fsl,imx31-ccm";
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reg = <0x53f80000 0x4000>;
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interrupts = <0 31 0x04 0 53 0x04>;
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#clock-cells = <1>;
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};
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};
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aips@53f00000 { /* AIPS2 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x53f00000 0x100000>;
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ranges;
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gpt: timer@53f90000 {
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compatible = "fsl,imx31-gpt";
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reg = <0x53f90000 0x4000>;
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interrupts = <29>;
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clocks = <&clks 10>, <&clks 22>;
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clock-names = "ipg", "per";
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};
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};
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};
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};
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