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da9d35e2f2
Brendan Jackman added extend atomic operations to the BPF instruction set in commit7064a7341a("Merge branch 'Atomics for eBPF'"), which introduces the BPF_ATOMIC_OP macro. However, that macro was missing for the BPF samples. Fix that by adding it into bpf_insn.h. Fixes:91c960b005("bpf: Rename BPF_XADD and prepare to encode other atomics in .imm") Signed-off-by: Björn Töpel <bjorn.topel@intel.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Brendan Jackman <jackmanb@google.com> Link: https://lore.kernel.org/bpf/20210118091753.107572-1-bjorn.topel@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
234 lines
6.3 KiB
C
234 lines
6.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* eBPF instruction mini library */
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#ifndef __BPF_INSN_H
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#define __BPF_INSN_H
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struct bpf_insn;
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/* ALU ops on registers, bpf_add|sub|...: dst_reg += src_reg */
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#define BPF_ALU64_REG(OP, DST, SRC) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_OP(OP) | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = 0 })
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#define BPF_ALU32_REG(OP, DST, SRC) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_OP(OP) | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = 0 })
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/* ALU ops on immediates, bpf_add|sub|...: dst_reg += imm32 */
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#define BPF_ALU64_IMM(OP, DST, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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#define BPF_ALU32_IMM(OP, DST, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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/* Short form of mov, dst_reg = src_reg */
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#define BPF_MOV64_REG(DST, SRC) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_MOV | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = 0 })
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#define BPF_MOV32_REG(DST, SRC) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_MOV | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = 0 })
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/* Short form of mov, dst_reg = imm32 */
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#define BPF_MOV64_IMM(DST, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_MOV | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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#define BPF_MOV32_IMM(DST, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_MOV | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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/* BPF_LD_IMM64 macro encodes single 'load 64-bit immediate' insn */
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#define BPF_LD_IMM64(DST, IMM) \
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BPF_LD_IMM64_RAW(DST, 0, IMM)
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#define BPF_LD_IMM64_RAW(DST, SRC, IMM) \
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((struct bpf_insn) { \
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.code = BPF_LD | BPF_DW | BPF_IMM, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = (__u32) (IMM) }), \
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((struct bpf_insn) { \
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.code = 0, /* zero is reserved opcode */ \
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.dst_reg = 0, \
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.src_reg = 0, \
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.off = 0, \
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.imm = ((__u64) (IMM)) >> 32 })
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#ifndef BPF_PSEUDO_MAP_FD
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# define BPF_PSEUDO_MAP_FD 1
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#endif
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/* pseudo BPF_LD_IMM64 insn used to refer to process-local map_fd */
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#define BPF_LD_MAP_FD(DST, MAP_FD) \
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BPF_LD_IMM64_RAW(DST, BPF_PSEUDO_MAP_FD, MAP_FD)
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/* Direct packet access, R0 = *(uint *) (skb->data + imm32) */
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#define BPF_LD_ABS(SIZE, IMM) \
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((struct bpf_insn) { \
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.code = BPF_LD | BPF_SIZE(SIZE) | BPF_ABS, \
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.dst_reg = 0, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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/* Memory load, dst_reg = *(uint *) (src_reg + off16) */
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#define BPF_LDX_MEM(SIZE, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_LDX | BPF_SIZE(SIZE) | BPF_MEM, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/* Memory store, *(uint *) (dst_reg + off16) = src_reg */
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#define BPF_STX_MEM(SIZE, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_STX | BPF_SIZE(SIZE) | BPF_MEM, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/*
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* Atomic operations:
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*
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* BPF_ADD *(uint *) (dst_reg + off16) += src_reg
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* BPF_AND *(uint *) (dst_reg + off16) &= src_reg
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* BPF_OR *(uint *) (dst_reg + off16) |= src_reg
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* BPF_XOR *(uint *) (dst_reg + off16) ^= src_reg
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* BPF_ADD | BPF_FETCH src_reg = atomic_fetch_add(dst_reg + off16, src_reg);
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* BPF_AND | BPF_FETCH src_reg = atomic_fetch_and(dst_reg + off16, src_reg);
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* BPF_OR | BPF_FETCH src_reg = atomic_fetch_or(dst_reg + off16, src_reg);
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* BPF_XOR | BPF_FETCH src_reg = atomic_fetch_xor(dst_reg + off16, src_reg);
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* BPF_XCHG src_reg = atomic_xchg(dst_reg + off16, src_reg)
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* BPF_CMPXCHG r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg)
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*/
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#define BPF_ATOMIC_OP(SIZE, OP, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_STX | BPF_SIZE(SIZE) | BPF_ATOMIC, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = OP })
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/* Legacy alias */
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#define BPF_STX_XADD(SIZE, DST, SRC, OFF) BPF_ATOMIC_OP(SIZE, BPF_ADD, DST, SRC, OFF)
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/* Memory store, *(uint *) (dst_reg + off16) = imm32 */
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#define BPF_ST_MEM(SIZE, DST, OFF, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ST | BPF_SIZE(SIZE) | BPF_MEM, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = OFF, \
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.imm = IMM })
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/* Conditional jumps against registers, if (dst_reg 'op' src_reg) goto pc + off16 */
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#define BPF_JMP_REG(OP, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_JMP | BPF_OP(OP) | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/* Like BPF_JMP_REG, but with 32-bit wide operands for comparison. */
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#define BPF_JMP32_REG(OP, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_JMP32 | BPF_OP(OP) | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/* Conditional jumps against immediates, if (dst_reg 'op' imm32) goto pc + off16 */
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#define BPF_JMP_IMM(OP, DST, IMM, OFF) \
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((struct bpf_insn) { \
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.code = BPF_JMP | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = OFF, \
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.imm = IMM })
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/* Like BPF_JMP_IMM, but with 32-bit wide operands for comparison. */
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#define BPF_JMP32_IMM(OP, DST, IMM, OFF) \
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((struct bpf_insn) { \
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.code = BPF_JMP32 | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = OFF, \
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.imm = IMM })
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/* Raw code statement block */
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#define BPF_RAW_INSN(CODE, DST, SRC, OFF, IMM) \
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((struct bpf_insn) { \
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.code = CODE, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = IMM })
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/* Program exit */
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#define BPF_EXIT_INSN() \
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((struct bpf_insn) { \
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.code = BPF_JMP | BPF_EXIT, \
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.dst_reg = 0, \
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.src_reg = 0, \
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.off = 0, \
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.imm = 0 })
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#endif
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