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f023f8dd59
This patch moves cpufreq driver of Samsung's ARM based s3c24xx platform to drivers/cpufreq. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
161 lines
3.7 KiB
C
161 lines
3.7 KiB
C
/*
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* Copyright (c) 2006-2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 CPU Frequency scaling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/cpufreq.h>
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include <plat/cpu-freq-core.h>
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/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
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static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
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{
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u32 clkdiv = 0;
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if (cfg->divs.h_divisor == 2)
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clkdiv |= S3C2410_CLKDIVN_HDIVN;
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if (cfg->divs.p_divisor != cfg->divs.h_divisor)
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clkdiv |= S3C2410_CLKDIVN_PDIVN;
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__raw_writel(clkdiv, S3C2410_CLKDIVN);
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}
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static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
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{
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unsigned long hclk, fclk, pclk;
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unsigned int hdiv, pdiv;
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unsigned long hclk_max;
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fclk = cfg->freq.fclk;
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hclk_max = cfg->max.hclk;
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cfg->freq.armclk = fclk;
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s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
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__func__, fclk, hclk_max);
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hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
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hclk = fclk / hdiv;
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if (hclk > cfg->max.hclk) {
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s3c_freq_dbg("%s: hclk too big\n", __func__);
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return -EINVAL;
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}
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pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
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pclk = hclk / pdiv;
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if (pclk > cfg->max.pclk) {
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s3c_freq_dbg("%s: pclk too big\n", __func__);
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return -EINVAL;
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}
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pdiv *= hdiv;
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/* record the result */
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cfg->divs.p_divisor = pdiv;
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cfg->divs.h_divisor = hdiv;
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return 0;
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}
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static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
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.max = {
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.fclk = 200000000,
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.hclk = 100000000,
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.pclk = 50000000,
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},
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/* transition latency is about 5ms worst-case, so
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* set 10ms to be sure */
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.latency = 10000000,
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.locktime_m = 150,
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.locktime_u = 150,
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.locktime_bits = 12,
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.need_pll = 1,
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.name = "s3c2410",
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.calc_iotiming = s3c2410_iotiming_calc,
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.set_iotiming = s3c2410_iotiming_set,
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.get_iotiming = s3c2410_iotiming_get,
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.resume_clocks = s3c2410_setup_clocks,
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.set_fvco = s3c2410_set_fvco,
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.set_refresh = s3c2410_cpufreq_setrefresh,
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.set_divs = s3c2410_cpufreq_setdivs,
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.calc_divs = s3c2410_cpufreq_calcdivs,
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.debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
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};
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static int s3c2410_cpufreq_add(struct device *dev,
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struct subsys_interface *sif)
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{
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return s3c_cpufreq_register(&s3c2410_cpufreq_info);
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}
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static struct subsys_interface s3c2410_cpufreq_interface = {
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.name = "s3c2410_cpufreq",
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.subsys = &s3c2410_subsys,
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.add_dev = s3c2410_cpufreq_add,
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};
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static int __init s3c2410_cpufreq_init(void)
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{
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return subsys_interface_register(&s3c2410_cpufreq_interface);
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}
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arch_initcall(s3c2410_cpufreq_init);
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static int s3c2410a_cpufreq_add(struct device *dev,
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struct subsys_interface *sif)
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{
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/* alter the maximum freq settings for S3C2410A. If a board knows
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* it only has a maximum of 200, then it should register its own
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* limits. */
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s3c2410_cpufreq_info.max.fclk = 266000000;
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s3c2410_cpufreq_info.max.hclk = 133000000;
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s3c2410_cpufreq_info.max.pclk = 66500000;
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s3c2410_cpufreq_info.name = "s3c2410a";
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return s3c2410_cpufreq_add(dev, sif);
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}
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static struct subsys_interface s3c2410a_cpufreq_interface = {
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.name = "s3c2410a_cpufreq",
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.subsys = &s3c2410a_subsys,
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.add_dev = s3c2410a_cpufreq_add,
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};
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static int __init s3c2410a_cpufreq_init(void)
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{
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return subsys_interface_register(&s3c2410a_cpufreq_interface);
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}
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arch_initcall(s3c2410a_cpufreq_init);
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