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fdd8b079e3
Symbols like SOFT_RESET are way too generic to be exported at large. To avoid this, let's move the mbus bridge register defines into a separate file and include it where needed. This affects mach-kirkwood, mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all share code in plat-orion which relies on those defines. Some other defines have been moved to narrower scopes, or simply deleted when they had no user. This fixes compilation problem with mpt2sas on the above listed platforms. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
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* arch/arm/mach-mv78xx0/irq.c
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*
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* MV78xx0 IRQ handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/gpio.h>
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#include <mach/bridge-regs.h>
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#include <plat/irq.h>
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#include "common.h"
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static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31);
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orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3);
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}
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void __init mv78xx0_init_irq(void)
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{
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int i;
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orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
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orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
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orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
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/*
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* Mask and clear GPIO IRQ interrupts.
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*/
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writel(0, GPIO_LEVEL_MASK(0));
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writel(0, GPIO_EDGE_MASK(0));
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writel(0, GPIO_EDGE_CAUSE(0));
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for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
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set_irq_chip(i, &orion_gpio_irq_chip);
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set_irq_handler(i, handle_level_irq);
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irq_desc[i].status |= IRQ_LEVEL;
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set_irq_flags(i, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
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set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
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set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
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set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
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}
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