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https://github.com/edk2-porting/linux-next.git
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60cd420c91
At one point in time all "future" platforms required three clocks, so the binding and driver was written to treat this as the default case. But new platforms has no clock requirements, which currently makes them all a special case, causing the need for a patch in the binding and driver for each new platform added. This patch reworks the driver logic so that it will attempt to acquire all three clocks and fail based on the given compatible. This allow us to drop the clock requirement from "qcom,scm", in a way that will remain backwards compatible with existing DT files. Specific compatibles are added for apq8084, msm8916 and msm8974 to match the updated binding and although equivalent to qcom,scm both ipq4019 and msm8996 are kept as these have been used without fallback to qcom,scm. The result of this patch is that new platforms, that require no clocks, can be use the fallback compatible of "qcom,scm". Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
641 lines
16 KiB
C
641 lines
16 KiB
C
/*
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* Qualcomm SCM driver
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*
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* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/cpumask.h>
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#include <linux/export.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/qcom_scm.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/reset-controller.h>
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#include "qcom_scm.h"
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static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
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module_param(download_mode, bool, 0);
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#define SCM_HAS_CORE_CLK BIT(0)
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#define SCM_HAS_IFACE_CLK BIT(1)
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#define SCM_HAS_BUS_CLK BIT(2)
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struct qcom_scm {
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struct device *dev;
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struct clk *core_clk;
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struct clk *iface_clk;
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struct clk *bus_clk;
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struct reset_controller_dev reset;
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u64 dload_mode_addr;
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};
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struct qcom_scm_current_perm_info {
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__le32 vmid;
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__le32 perm;
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__le64 ctx;
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__le32 ctx_size;
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__le32 unused;
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};
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struct qcom_scm_mem_map_info {
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__le64 mem_addr;
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__le64 mem_size;
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};
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static struct qcom_scm *__scm;
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static int qcom_scm_clk_enable(void)
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{
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int ret;
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ret = clk_prepare_enable(__scm->core_clk);
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if (ret)
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goto bail;
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ret = clk_prepare_enable(__scm->iface_clk);
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if (ret)
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goto disable_core;
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ret = clk_prepare_enable(__scm->bus_clk);
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if (ret)
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goto disable_iface;
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return 0;
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disable_iface:
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clk_disable_unprepare(__scm->iface_clk);
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disable_core:
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clk_disable_unprepare(__scm->core_clk);
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bail:
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return ret;
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}
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static void qcom_scm_clk_disable(void)
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{
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clk_disable_unprepare(__scm->core_clk);
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clk_disable_unprepare(__scm->iface_clk);
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clk_disable_unprepare(__scm->bus_clk);
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}
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/**
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* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the cold boot address of the cpus. Any cpu outside the supported
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* range would be removed from the cpu present mask.
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*/
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int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return __qcom_scm_set_cold_boot_addr(entry, cpus);
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}
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EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
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/**
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* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the Linux entry point for the SCM to transfer control to when coming
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* out of a power down. CPU power down may be executed on cpuidle or hotplug.
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*/
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int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return __qcom_scm_set_warm_boot_addr(__scm->dev, entry, cpus);
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}
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EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
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/**
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* qcom_scm_cpu_power_down() - Power down the cpu
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* @flags - Flags to flush cache
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*
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* This is an end point to power down cpu. If there was a pending interrupt,
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* the control would return from this function, otherwise, the cpu jumps to the
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* warm boot entry point set for this cpu upon reset.
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*/
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void qcom_scm_cpu_power_down(u32 flags)
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{
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__qcom_scm_cpu_power_down(flags);
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}
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EXPORT_SYMBOL(qcom_scm_cpu_power_down);
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/**
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* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
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*
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* Return true if HDCP is supported, false if not.
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*/
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bool qcom_scm_hdcp_available(void)
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{
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int ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
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QCOM_SCM_CMD_HDCP);
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qcom_scm_clk_disable();
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return ret > 0 ? true : false;
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}
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EXPORT_SYMBOL(qcom_scm_hdcp_available);
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/**
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* qcom_scm_hdcp_req() - Send HDCP request.
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* @req: HDCP request array
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* @req_cnt: HDCP request array count
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* @resp: response buffer passed to SCM
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*
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* Write HDCP register(s) through SCM.
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*/
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int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
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{
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int ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_hdcp_req);
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/**
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* qcom_scm_pas_supported() - Check if the peripheral authentication service is
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* available for the given peripherial
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* @peripheral: peripheral id
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*
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* Returns true if PAS is supported for this peripheral, otherwise false.
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*/
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bool qcom_scm_pas_supported(u32 peripheral)
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{
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int ret;
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ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_IS_SUPPORTED_CMD);
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if (ret <= 0)
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return false;
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return __qcom_scm_pas_supported(__scm->dev, peripheral);
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}
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EXPORT_SYMBOL(qcom_scm_pas_supported);
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/**
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* qcom_scm_pas_init_image() - Initialize peripheral authentication service
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* state machine for a given peripheral, using the
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* metadata
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* @peripheral: peripheral id
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* @metadata: pointer to memory containing ELF header, program header table
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* and optional blob of data used for authenticating the metadata
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* and the rest of the firmware
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* @size: size of the metadata
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
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{
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dma_addr_t mdata_phys;
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void *mdata_buf;
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int ret;
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/*
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* During the scm call memory protection will be enabled for the meta
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* data blob, so make sure it's physically contiguous, 4K aligned and
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* non-cachable to avoid XPU violations.
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*/
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mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
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GFP_KERNEL);
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if (!mdata_buf) {
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dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
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return -ENOMEM;
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}
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memcpy(mdata_buf, metadata, size);
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ret = qcom_scm_clk_enable();
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if (ret)
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goto free_metadata;
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ret = __qcom_scm_pas_init_image(__scm->dev, peripheral, mdata_phys);
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qcom_scm_clk_disable();
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free_metadata:
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dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_pas_init_image);
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/**
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* qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
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* for firmware loading
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* @peripheral: peripheral id
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* @addr: start address of memory area to prepare
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* @size: size of the memory area to prepare
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
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{
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int ret;
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ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_pas_mem_setup(__scm->dev, peripheral, addr, size);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
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/**
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* qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
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* and reset the remote processor
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* @peripheral: peripheral id
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*
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* Return 0 on success.
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*/
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int qcom_scm_pas_auth_and_reset(u32 peripheral)
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{
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int ret;
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ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_pas_auth_and_reset(__scm->dev, peripheral);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
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/**
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* qcom_scm_pas_shutdown() - Shut down the remote processor
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* @peripheral: peripheral id
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_shutdown(u32 peripheral)
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{
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int ret;
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ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_pas_shutdown(__scm->dev, peripheral);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_pas_shutdown);
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static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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if (idx != 0)
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return -EINVAL;
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return __qcom_scm_pas_mss_reset(__scm->dev, 1);
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}
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static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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if (idx != 0)
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return -EINVAL;
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return __qcom_scm_pas_mss_reset(__scm->dev, 0);
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}
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static const struct reset_control_ops qcom_scm_pas_reset_ops = {
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.assert = qcom_scm_pas_reset_assert,
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.deassert = qcom_scm_pas_reset_deassert,
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};
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int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
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{
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return __qcom_scm_restore_sec_cfg(__scm->dev, device_id, spare);
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}
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EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
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int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
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{
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return __qcom_scm_iommu_secure_ptbl_size(__scm->dev, spare, size);
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}
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EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
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int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
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{
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return __qcom_scm_iommu_secure_ptbl_init(__scm->dev, addr, size, spare);
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}
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EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
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int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
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{
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return __qcom_scm_io_readl(__scm->dev, addr, val);
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}
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EXPORT_SYMBOL(qcom_scm_io_readl);
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int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
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{
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return __qcom_scm_io_writel(__scm->dev, addr, val);
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}
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EXPORT_SYMBOL(qcom_scm_io_writel);
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static void qcom_scm_set_download_mode(bool enable)
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{
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bool avail;
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int ret = 0;
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avail = __qcom_scm_is_call_available(__scm->dev,
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QCOM_SCM_SVC_BOOT,
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QCOM_SCM_SET_DLOAD_MODE);
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if (avail) {
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ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
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} else if (__scm->dload_mode_addr) {
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ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
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enable ? QCOM_SCM_SET_DLOAD_MODE : 0);
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} else {
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dev_err(__scm->dev,
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"No available mechanism for setting download mode\n");
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}
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if (ret)
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dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
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}
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static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
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{
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struct device_node *tcsr;
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struct device_node *np = dev->of_node;
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struct resource res;
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u32 offset;
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int ret;
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tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
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if (!tcsr)
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return 0;
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ret = of_address_to_resource(tcsr, 0, &res);
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of_node_put(tcsr);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
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if (ret < 0)
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return ret;
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*addr = res.start + offset;
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return 0;
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}
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/**
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* qcom_scm_is_available() - Checks if SCM is available
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*/
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bool qcom_scm_is_available(void)
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{
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return !!__scm;
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}
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EXPORT_SYMBOL(qcom_scm_is_available);
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int qcom_scm_set_remote_state(u32 state, u32 id)
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{
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return __qcom_scm_set_remote_state(__scm->dev, state, id);
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}
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EXPORT_SYMBOL(qcom_scm_set_remote_state);
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/**
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* qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
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* @mem_addr: mem region whose ownership need to be reassigned
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* @mem_sz: size of the region.
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* @srcvm: vmid for current set of owners, each set bit in
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* flag indicate a unique owner
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* @newvm: array having new owners and corrsponding permission
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* flags
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* @dest_cnt: number of owners in next set.
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*
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* Return negative errno on failure, 0 on success, with @srcvm updated.
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*/
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int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *srcvm,
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struct qcom_scm_vmperm *newvm, int dest_cnt)
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{
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struct qcom_scm_current_perm_info *destvm;
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struct qcom_scm_mem_map_info *mem_to_map;
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phys_addr_t mem_to_map_phys;
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phys_addr_t dest_phys;
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phys_addr_t ptr_phys;
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size_t mem_to_map_sz;
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size_t dest_sz;
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size_t src_sz;
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size_t ptr_sz;
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int next_vm;
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__le32 *src;
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void *ptr;
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int ret;
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int len;
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int i;
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src_sz = hweight_long(*srcvm) * sizeof(*src);
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mem_to_map_sz = sizeof(*mem_to_map);
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dest_sz = dest_cnt * sizeof(*destvm);
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ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +
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ALIGN(dest_sz, SZ_64);
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ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);
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if (!ptr)
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return -ENOMEM;
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/* Fill source vmid detail */
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src = ptr;
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len = hweight_long(*srcvm);
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for (i = 0; i < len; i++) {
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src[i] = cpu_to_le32(ffs(*srcvm) - 1);
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*srcvm ^= 1 << (ffs(*srcvm) - 1);
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}
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/* Fill details of mem buff to map */
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mem_to_map = ptr + ALIGN(src_sz, SZ_64);
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mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);
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mem_to_map[0].mem_addr = cpu_to_le64(mem_addr);
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mem_to_map[0].mem_size = cpu_to_le64(mem_sz);
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next_vm = 0;
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/* Fill details of next vmid detail */
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destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
|
|
dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
|
|
for (i = 0; i < dest_cnt; i++) {
|
|
destvm[i].vmid = cpu_to_le32(newvm[i].vmid);
|
|
destvm[i].perm = cpu_to_le32(newvm[i].perm);
|
|
destvm[i].ctx = 0;
|
|
destvm[i].ctx_size = 0;
|
|
next_vm |= BIT(newvm[i].vmid);
|
|
}
|
|
|
|
ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,
|
|
ptr_phys, src_sz, dest_phys, dest_sz);
|
|
dma_free_coherent(__scm->dev, ALIGN(ptr_sz, SZ_64), ptr, ptr_phys);
|
|
if (ret) {
|
|
dev_err(__scm->dev,
|
|
"Assign memory protection call failed %d.\n", ret);
|
|
return -EINVAL;
|
|
}
|
|
|
|
*srcvm = next_vm;
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_assign_mem);
|
|
|
|
static int qcom_scm_probe(struct platform_device *pdev)
|
|
{
|
|
struct qcom_scm *scm;
|
|
unsigned long clks;
|
|
int ret;
|
|
|
|
scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
|
|
if (!scm)
|
|
return -ENOMEM;
|
|
|
|
ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
clks = (unsigned long)of_device_get_match_data(&pdev->dev);
|
|
|
|
scm->core_clk = devm_clk_get(&pdev->dev, "core");
|
|
if (IS_ERR(scm->core_clk)) {
|
|
if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
|
|
return PTR_ERR(scm->core_clk);
|
|
|
|
if (clks & SCM_HAS_CORE_CLK) {
|
|
dev_err(&pdev->dev, "failed to acquire core clk\n");
|
|
return PTR_ERR(scm->core_clk);
|
|
}
|
|
|
|
scm->core_clk = NULL;
|
|
}
|
|
|
|
scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
|
|
if (IS_ERR(scm->iface_clk)) {
|
|
if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER)
|
|
return PTR_ERR(scm->iface_clk);
|
|
|
|
if (clks & SCM_HAS_IFACE_CLK) {
|
|
dev_err(&pdev->dev, "failed to acquire iface clk\n");
|
|
return PTR_ERR(scm->iface_clk);
|
|
}
|
|
|
|
scm->iface_clk = NULL;
|
|
}
|
|
|
|
scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
|
|
if (IS_ERR(scm->bus_clk)) {
|
|
if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER)
|
|
return PTR_ERR(scm->bus_clk);
|
|
|
|
if (clks & SCM_HAS_BUS_CLK) {
|
|
dev_err(&pdev->dev, "failed to acquire bus clk\n");
|
|
return PTR_ERR(scm->bus_clk);
|
|
}
|
|
|
|
scm->bus_clk = NULL;
|
|
}
|
|
|
|
scm->reset.ops = &qcom_scm_pas_reset_ops;
|
|
scm->reset.nr_resets = 1;
|
|
scm->reset.of_node = pdev->dev.of_node;
|
|
ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* vote for max clk rate for highest performance */
|
|
ret = clk_set_rate(scm->core_clk, INT_MAX);
|
|
if (ret)
|
|
return ret;
|
|
|
|
__scm = scm;
|
|
__scm->dev = &pdev->dev;
|
|
|
|
__qcom_scm_init();
|
|
|
|
/*
|
|
* If requested enable "download mode", from this point on warmboot
|
|
* will cause the the boot stages to enter download mode, unless
|
|
* disabled below by a clean shutdown/reboot.
|
|
*/
|
|
if (download_mode)
|
|
qcom_scm_set_download_mode(true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void qcom_scm_shutdown(struct platform_device *pdev)
|
|
{
|
|
/* Clean shutdown, disable download mode to allow normal restart */
|
|
if (download_mode)
|
|
qcom_scm_set_download_mode(false);
|
|
}
|
|
|
|
static const struct of_device_id qcom_scm_dt_match[] = {
|
|
{ .compatible = "qcom,scm-apq8064",
|
|
/* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
|
|
},
|
|
{ .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK |
|
|
SCM_HAS_IFACE_CLK |
|
|
SCM_HAS_BUS_CLK)
|
|
},
|
|
{ .compatible = "qcom,scm-ipq4019" },
|
|
{ .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
|
|
{ .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
|
|
{ .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
|
|
SCM_HAS_IFACE_CLK |
|
|
SCM_HAS_BUS_CLK)
|
|
},
|
|
{ .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
|
|
SCM_HAS_IFACE_CLK |
|
|
SCM_HAS_BUS_CLK)
|
|
},
|
|
{ .compatible = "qcom,scm-msm8996" },
|
|
{ .compatible = "qcom,scm" },
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver qcom_scm_driver = {
|
|
.driver = {
|
|
.name = "qcom_scm",
|
|
.of_match_table = qcom_scm_dt_match,
|
|
},
|
|
.probe = qcom_scm_probe,
|
|
.shutdown = qcom_scm_shutdown,
|
|
};
|
|
|
|
static int __init qcom_scm_init(void)
|
|
{
|
|
return platform_driver_register(&qcom_scm_driver);
|
|
}
|
|
subsys_initcall(qcom_scm_init);
|