mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 06:34:11 +08:00
dfd10e7ae6
New core SoC-specific changes.
New platforms:
* Introduction of a vendor, Hisilicon, and one of their SoCs with some
random numerical product name.
* Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m, i.e. !MMU).
* Marvell Berlin series of SoCs, which include the one in Chromecast.
* MOXA platform support, ARM9-based platform used mostly in industrial products
* Support for Freescale's i.MX50 SoC.
Other work:
* Renesas work for new platforms and drivers, and conversion over to
more multiplatform-friendly device registration schemes.
* SMP support for Allwinner sunxi platforms.
* ... plus a bunch of other stuff across various platforms.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJS4VggAAoJEIwa5zzehBx3YkEP/j/Vp83zPcPijb8CNLUGJ9rK
RTOW9hlLbwCGAcIi/32XVjup1ylTzQuwKpH2R6Sf2GRcmXI1HbCCyDSGKWq+eK9C
vDRoWiU9DVRmXuaC7R1dscLS1qSobVoI80bOstblZW65799z48IllD7rJA1BzDIg
vUy4knY9hO39DK7sJymXTBJepWxXJHMaYmr15xuxbaR3Qsp8zisqyzMwLqVfBwFB
FyPr2PfxU8HJOoWhIsVo+679pmb9tHD6our0HG/lHSuPcRO/3UwN+VD87SwfpjNx
P7qiRFkIoMooiTRmjwPPNbMZBJHl6vBR1RWHmws5s9aay1DDhdvQURxKx4bNaN/A
UzwiestopISLChd9jqjxTbngl1mvLaL9JwBjRVAkXG4vJJFrhwqvmcMrlszA3ueR
2Th/NBk0b2s8ncAuT7bFe4i/H7es8aI/D2weF3FxRGgpan/B0T0UDAKO+rrMYZ0q
1ZoqlgMQZ0o1l7B5v90h0QQo/GMmin1xzyAChmsl8xbOHh5YfWVFGwLzVbYeZ/YJ
yf3CcgQjAA8UV3f1J3nZeqM84o8qqtKUmUjsqWIgT2DnxOoM3pGckrmQ4OvhLccd
etROW2nr8EqmoL7shheeHPANoDsTT1XSs0xbWo4ZBpGW5rTIFVoLEGyqa48tw5qA
pkH1KwpwEXTrw6MXP5L1
=pgLW
-----END PGP SIGNATURE-----
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"New core SoC-specific changes.
New platforms:
* Introduction of a vendor, Hisilicon, and one of their SoCs with
some random numerical product name.
* Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m,
i.e. !MMU).
* Marvell Berlin series of SoCs, which include the one in Chromecast.
* MOXA platform support, ARM9-based platform used mostly in
industrial products
* Support for Freescale's i.MX50 SoC.
Other work:
* Renesas work for new platforms and drivers, and conversion over to
more multiplatform-friendly device registration schemes.
* SMP support for Allwinner sunxi platforms.
* ... plus a bunch of other stuff across various platforms"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits)
ARM: tegra: fix tegra_powergate_sequence_power_up() inline
ARM: msm_defconfig: Update for multi-platform
ARM: msm: Move MSM's DT based hardware to multi-platform support
ARM: msm: Only build timer.c if required
ARM: msm: Only build clock.c on proc_comm based platforms
ARM: ux500: Enable system suspend with WFI support
ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
ARM: shmobile: r8a7790: Fix I2C controller names
ARM: msm: Simplify ARCH_MSM_DT config
ARM: msm: Add support for MSM8974 SoC
ARM: sunxi: select ARM_PSCI
MAINTAINERS: Update Allwinner sunXi maintainer files
ARM: sunxi: Select RESET_CONTROLLER
ARM: imx: improve the comment of CCM lpm SW workaround
ARM: imx: improve status check of clock gate
ARM: imx: add necessary interface for pfd
ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
ARM: imx: Add cpu frequency scaling support
ARM i.MX35: Add devicetree support.
...
244 lines
7.3 KiB
C
244 lines
7.3 KiB
C
/*
|
|
* r8a7790 processor support
|
|
*
|
|
* Copyright (C) 2013 Renesas Solutions Corp.
|
|
* Copyright (C) 2013 Magnus Damm
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
*/
|
|
|
|
#include <linux/irq.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/of_platform.h>
|
|
#include <linux/platform_data/gpio-rcar.h>
|
|
#include <linux/platform_data/irq-renesas-irqc.h>
|
|
#include <linux/serial_sci.h>
|
|
#include <linux/sh_timer.h>
|
|
#include <mach/common.h>
|
|
#include <mach/irqs.h>
|
|
#include <mach/r8a7790.h>
|
|
#include <asm/mach/arch.h>
|
|
|
|
static const struct resource pfc_resources[] __initconst = {
|
|
DEFINE_RES_MEM(0xe6060000, 0x250),
|
|
};
|
|
|
|
#define r8a7790_register_pfc() \
|
|
platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
|
|
ARRAY_SIZE(pfc_resources))
|
|
|
|
#define R8A7790_GPIO(idx) \
|
|
static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
|
|
DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
|
|
DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
|
|
}; \
|
|
\
|
|
static const struct gpio_rcar_config \
|
|
r8a7790_gpio##idx##_platform_data __initconst = { \
|
|
.gpio_base = 32 * (idx), \
|
|
.irq_base = 0, \
|
|
.number_of_pins = 32, \
|
|
.pctl_name = "pfc-r8a7790", \
|
|
.has_both_edge_trigger = 1, \
|
|
}; \
|
|
|
|
R8A7790_GPIO(0);
|
|
R8A7790_GPIO(1);
|
|
R8A7790_GPIO(2);
|
|
R8A7790_GPIO(3);
|
|
R8A7790_GPIO(4);
|
|
R8A7790_GPIO(5);
|
|
|
|
#define r8a7790_register_gpio(idx) \
|
|
platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
|
|
r8a7790_gpio##idx##_resources, \
|
|
ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
|
|
&r8a7790_gpio##idx##_platform_data, \
|
|
sizeof(r8a7790_gpio##idx##_platform_data))
|
|
|
|
static struct resource i2c_resources[] __initdata = {
|
|
/* I2C0 */
|
|
DEFINE_RES_MEM(0xE6508000, 0x40),
|
|
DEFINE_RES_IRQ(gic_spi(287)),
|
|
/* I2C1 */
|
|
DEFINE_RES_MEM(0xE6518000, 0x40),
|
|
DEFINE_RES_IRQ(gic_spi(288)),
|
|
/* I2C2 */
|
|
DEFINE_RES_MEM(0xE6530000, 0x40),
|
|
DEFINE_RES_IRQ(gic_spi(286)),
|
|
/* I2C3 */
|
|
DEFINE_RES_MEM(0xE6540000, 0x40),
|
|
DEFINE_RES_IRQ(gic_spi(290)),
|
|
|
|
};
|
|
|
|
#define r8a7790_register_i2c(idx) \
|
|
platform_device_register_simple( \
|
|
"i2c-rcar_gen2", idx, \
|
|
i2c_resources + (2 * idx), 2); \
|
|
|
|
void __init r8a7790_pinmux_init(void)
|
|
{
|
|
r8a7790_register_pfc();
|
|
r8a7790_register_gpio(0);
|
|
r8a7790_register_gpio(1);
|
|
r8a7790_register_gpio(2);
|
|
r8a7790_register_gpio(3);
|
|
r8a7790_register_gpio(4);
|
|
r8a7790_register_gpio(5);
|
|
r8a7790_register_i2c(0);
|
|
r8a7790_register_i2c(1);
|
|
r8a7790_register_i2c(2);
|
|
r8a7790_register_i2c(3);
|
|
}
|
|
|
|
#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
|
|
static struct plat_sci_port scif##index##_platform_data = { \
|
|
.type = scif_type, \
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
|
|
.scscr = _scscr, \
|
|
}; \
|
|
\
|
|
static struct resource scif##index##_resources[] = { \
|
|
DEFINE_RES_MEM(baseaddr, 0x100), \
|
|
DEFINE_RES_IRQ(irq), \
|
|
}
|
|
|
|
#define R8A7790_SCIF(index, baseaddr, irq) \
|
|
__R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
|
|
index, baseaddr, irq)
|
|
|
|
#define R8A7790_SCIFA(index, baseaddr, irq) \
|
|
__R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
|
|
index, baseaddr, irq)
|
|
|
|
#define R8A7790_SCIFB(index, baseaddr, irq) \
|
|
__R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
|
|
index, baseaddr, irq)
|
|
|
|
#define R8A7790_HSCIF(index, baseaddr, irq) \
|
|
__R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
|
|
index, baseaddr, irq)
|
|
|
|
R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
|
|
R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
|
|
R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
|
|
R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
|
|
R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
|
|
R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
|
|
R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
|
|
R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
|
|
R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
|
|
R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
|
|
|
|
#define r8a7790_register_scif(index) \
|
|
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
|
|
scif##index##_resources, \
|
|
ARRAY_SIZE(scif##index##_resources), \
|
|
&scif##index##_platform_data, \
|
|
sizeof(scif##index##_platform_data))
|
|
|
|
static const struct renesas_irqc_config irqc0_data __initconst = {
|
|
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
|
|
};
|
|
|
|
static const struct resource irqc0_resources[] __initconst = {
|
|
DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
|
|
DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
|
|
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
|
|
DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
|
|
DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
|
|
};
|
|
|
|
#define r8a7790_register_irqc(idx) \
|
|
platform_device_register_resndata(&platform_bus, "renesas_irqc", \
|
|
idx, irqc##idx##_resources, \
|
|
ARRAY_SIZE(irqc##idx##_resources), \
|
|
&irqc##idx##_data, \
|
|
sizeof(struct renesas_irqc_config))
|
|
|
|
static const struct resource thermal_resources[] __initconst = {
|
|
DEFINE_RES_MEM(0xe61f0000, 0x14),
|
|
DEFINE_RES_MEM(0xe61f0100, 0x38),
|
|
DEFINE_RES_IRQ(gic_spi(69)),
|
|
};
|
|
|
|
#define r8a7790_register_thermal() \
|
|
platform_device_register_simple("rcar_thermal", -1, \
|
|
thermal_resources, \
|
|
ARRAY_SIZE(thermal_resources))
|
|
|
|
static const struct sh_timer_config cmt00_platform_data __initconst = {
|
|
.name = "CMT00",
|
|
.timer_bit = 0,
|
|
.clockevent_rating = 80,
|
|
};
|
|
|
|
static const struct resource cmt00_resources[] __initconst = {
|
|
DEFINE_RES_MEM(0xffca0510, 0x0c),
|
|
DEFINE_RES_MEM(0xffca0500, 0x04),
|
|
DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
|
|
};
|
|
|
|
#define r8a7790_register_cmt(idx) \
|
|
platform_device_register_resndata(&platform_bus, "sh_cmt", \
|
|
idx, cmt##idx##_resources, \
|
|
ARRAY_SIZE(cmt##idx##_resources), \
|
|
&cmt##idx##_platform_data, \
|
|
sizeof(struct sh_timer_config))
|
|
|
|
void __init r8a7790_add_dt_devices(void)
|
|
{
|
|
r8a7790_register_scif(0);
|
|
r8a7790_register_scif(1);
|
|
r8a7790_register_scif(2);
|
|
r8a7790_register_scif(3);
|
|
r8a7790_register_scif(4);
|
|
r8a7790_register_scif(5);
|
|
r8a7790_register_scif(6);
|
|
r8a7790_register_scif(7);
|
|
r8a7790_register_scif(8);
|
|
r8a7790_register_scif(9);
|
|
r8a7790_register_cmt(00);
|
|
}
|
|
|
|
void __init r8a7790_add_standard_devices(void)
|
|
{
|
|
r8a7790_add_dt_devices();
|
|
r8a7790_register_irqc(0);
|
|
r8a7790_register_thermal();
|
|
}
|
|
|
|
void __init r8a7790_init_early(void)
|
|
{
|
|
#ifndef CONFIG_ARM_ARCH_TIMER
|
|
shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_USE_OF
|
|
|
|
static const char * const r8a7790_boards_compat_dt[] __initconst = {
|
|
"renesas,r8a7790",
|
|
NULL,
|
|
};
|
|
|
|
DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
|
|
.smp = smp_ops(r8a7790_smp_ops),
|
|
.init_early = r8a7790_init_early,
|
|
.init_time = rcar_gen2_timer_init,
|
|
.dt_compat = r8a7790_boards_compat_dt,
|
|
MACHINE_END
|
|
#endif /* CONFIG_USE_OF */
|