Rex Zhu b02d4081a5 drm/amdgpu: refine cz uvd clock gate logic. ... sw clockgate was used on uvd6.0. when uvd is idle, we gate the uvd clock. when decode, we ungate the uvd clock. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2016-11-23 15:08:39 -05:00
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drm	drm/amdgpu: refine cz uvd clock gate logic.	2016-11-23 15:08:39 -05:00
host1x	drm/tegra: dsi: Enhance runtime power management	2016-08-24 15:58:57 +02:00
ipu-v3	imx-drm plane update cleanup, YUV formats	2016-11-11 09:31:27 +10:00
vga	drivers/gpu/vga: allocate vga_arb_write() buffer on stack	2016-10-17 08:21:14 +02:00
Makefile