mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 20:53:53 +08:00
04a39c577f
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
624 lines
21 KiB
C
624 lines
21 KiB
C
/*
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* Copyright 2003 NVIDIA, Corporation
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* Copyright 2006 Dave Airlie
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* Copyright 2007 Maarten Maathuis
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* Copyright 2007-2009 Stuart Bennett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm_crtc_helper.h"
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#include "nouveau_drv.h"
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#include "nouveau_encoder.h"
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#include "nouveau_connector.h"
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#include "nouveau_crtc.h"
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#include "nouveau_hw.h"
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#include "nvreg.h"
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#define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \
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NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \
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NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
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#define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \
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NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \
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NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
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static inline bool is_fpc_off(uint32_t fpc)
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{
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return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
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FP_TG_CONTROL_OFF);
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}
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int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent)
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{
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/* special case of nv_read_tmds to find crtc associated with an output.
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* this does not give a correct answer for off-chip dvi, but there's no
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* use for such an answer anyway
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*/
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int ramdac = (dcbent->or & OUTPUT_C) >> 2;
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NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
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NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
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return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
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}
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void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
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int head, bool dl)
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{
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/* The BIOS scripts don't do this for us, sadly
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* Luckily we do know the values ;-)
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*
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* head < 0 indicates we wish to force a setting with the overrideval
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* (for VT restore etc.)
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*/
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int ramdac = (dcbent->or & OUTPUT_C) >> 2;
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uint8_t tmds04 = 0x80;
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if (head != ramdac)
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tmds04 = 0x88;
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if (dcbent->type == OUTPUT_LVDS)
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tmds04 |= 0x01;
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nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
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if (dl) /* dual link */
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nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
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}
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void nv04_dfp_disable(struct drm_device *dev, int head)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
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if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
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FP_TG_CONTROL_ON) {
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/* digital remnants must be cleaned before new crtc
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* values programmed. delay is time for the vga stuff
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* to realise it's in control again
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*/
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
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FP_TG_CONTROL_OFF);
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msleep(50);
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}
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/* don't inadvertently turn it on when state written later */
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crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
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}
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void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc;
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struct nouveau_crtc *nv_crtc;
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uint32_t *fpc;
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if (mode == DRM_MODE_DPMS_ON) {
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nv_crtc = nouveau_crtc(encoder->crtc);
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fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
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if (is_fpc_off(*fpc)) {
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/* using saved value is ok, as (is_digital && dpms_on &&
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* fp_control==OFF) is (at present) *only* true when
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* fpc's most recent change was by below "off" code
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*/
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*fpc = nv_crtc->dpms_saved_fp_control;
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}
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nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
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NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
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} else {
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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nv_crtc = nouveau_crtc(crtc);
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fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
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nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
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if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
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nv_crtc->dpms_saved_fp_control = *fpc;
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/* cut the FP output */
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*fpc &= ~FP_TG_CONTROL_ON;
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*fpc |= FP_TG_CONTROL_OFF;
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NVWriteRAMDAC(dev, nv_crtc->index,
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NV_PRAMDAC_FP_TG_CONTROL, *fpc);
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}
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}
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}
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}
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static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
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/* For internal panels and gpu scaling on DVI we need the native mode */
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if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
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if (!nv_connector->native_mode)
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return false;
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nv_encoder->mode = *nv_connector->native_mode;
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adjusted_mode->clock = nv_connector->native_mode->clock;
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} else {
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nv_encoder->mode = *adjusted_mode;
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}
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return true;
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}
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static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
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struct nouveau_encoder *nv_encoder, int head)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv04_mode_state *state = &dev_priv->mode_reg;
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uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
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if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
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return;
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/* SEL_CLK is only used on the primary ramdac
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* It toggles spread spectrum PLL output and sets the bindings of PLLs
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* to heads on digital outputs
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*/
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if (head)
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state->sel_clk |= bits1618;
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else
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state->sel_clk &= ~bits1618;
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/* nv30:
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* bit 0 NVClk spread spectrum on/off
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* bit 2 MemClk spread spectrum on/off
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* bit 4 PixClk1 spread spectrum on/off toggle
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* bit 6 PixClk2 spread spectrum on/off toggle
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*
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* nv40 (observations from bios behaviour and mmio traces):
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* bits 4&6 as for nv30
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* bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6;
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* maybe a different spread mode
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* bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
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* The logic behind turning spread spectrum on/off in the first place,
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* and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
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* entry has the necessary info)
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*/
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if (nv_encoder->dcb->type == OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) {
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int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1;
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state->sel_clk &= ~0xf0;
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state->sel_clk |= (head ? 0x40 : 0x10) << shift;
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}
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}
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static void nv04_dfp_prepare(struct drm_encoder *encoder)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_encoder_helper_funcs *helper = encoder->helper_private;
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int head = nouveau_crtc(encoder->crtc)->index;
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struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
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uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
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uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
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helper->dpms(encoder, DRM_MODE_DPMS_OFF);
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nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
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/* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
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* at LCD__INDEX which we don't alter
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*/
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if (!(*cr_lcd & 0x44)) {
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*cr_lcd = 0x3;
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if (nv_two_heads(dev)) {
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if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
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*cr_lcd |= head ? 0x0 : 0x8;
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else {
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*cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
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if (nv_encoder->dcb->type == OUTPUT_LVDS)
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*cr_lcd |= 0x30;
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if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
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/* avoid being connected to both crtcs */
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*cr_lcd_oth &= ~0x30;
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NVWriteVgaCrtc(dev, head ^ 1,
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NV_CIO_CRE_LCD__INDEX,
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*cr_lcd_oth);
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}
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}
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}
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}
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}
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static void nv04_dfp_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
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struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
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struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
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struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_display_mode *output_mode = &nv_encoder->mode;
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uint32_t mode_ratio, panel_ratio;
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NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
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drm_mode_debug_printmodeline(output_mode);
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/* Initialize the FP registers in this CRTC. */
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regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
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regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
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if (!nv_gf4_disp_arch(dev) ||
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(output_mode->hsync_start - output_mode->hdisplay) >=
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dev_priv->vbios.digital_min_front_porch)
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regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
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else
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regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1;
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regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
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regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
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regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
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regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
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regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
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regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
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regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
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regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
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regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
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regp->fp_vert_regs[FP_VALID_START] = 0;
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regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
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/* bit26: a bit seen on some g7x, no as yet discernable purpose */
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regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
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(savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
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/* Deal with vsync/hsync polarity */
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/* LVDS screens do set this, but modes with +ve syncs are very rare */
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if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
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regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
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if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
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regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
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/* panel scaling first, as native would get set otherwise */
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if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
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nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */
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regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
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else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
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adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
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regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
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else /* gpu needs to scale */
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regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
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if (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
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regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
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if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
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output_mode->clock > 165000)
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regp->fp_control |= (2 << 24);
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if (nv_encoder->dcb->type == OUTPUT_LVDS) {
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bool duallink, dummy;
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nouveau_bios_parse_lvds_table(dev, nv_connector->native_mode->
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clock, &duallink, &dummy);
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if (duallink)
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regp->fp_control |= (8 << 28);
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} else
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if (output_mode->clock > 165000)
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regp->fp_control |= (8 << 28);
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regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
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NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
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NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
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NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
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NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
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NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
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NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
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/* We want automatic scaling */
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regp->fp_debug_1 = 0;
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/* This can override HTOTAL and VTOTAL */
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regp->fp_debug_2 = 0;
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/* Use 20.12 fixed point format to avoid floats */
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mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
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panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
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/* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
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* get treated the same as SCALE_FULLSCREEN */
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if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
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mode_ratio != panel_ratio) {
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uint32_t diff, scale;
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bool divide_by_2 = nv_gf4_disp_arch(dev);
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if (mode_ratio < panel_ratio) {
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/* vertical needs to expand to glass size (automatic)
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* horizontal needs to be scaled at vertical scale factor
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* to maintain aspect */
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scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
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regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
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XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
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/* restrict area of screen used, horizontally */
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diff = output_mode->hdisplay -
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output_mode->vdisplay * mode_ratio / (1 << 12);
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regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
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regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
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}
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if (mode_ratio > panel_ratio) {
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/* horizontal needs to expand to glass size (automatic)
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* vertical needs to be scaled at horizontal scale factor
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* to maintain aspect */
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scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
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regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
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XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
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/* restrict area of screen used, vertically */
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diff = output_mode->vdisplay -
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(1 << 12) * output_mode->hdisplay / mode_ratio;
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regp->fp_vert_regs[FP_VALID_START] += diff / 2;
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regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
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}
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}
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/* Output property. */
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if (nv_connector->use_dithering) {
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if (dev_priv->chipset == 0x11)
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regp->dither = savep->dither | 0x00010000;
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else {
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int i;
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regp->dither = savep->dither | 0x00000001;
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for (i = 0; i < 3; i++) {
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regp->dither_regs[i] = 0xe4e4e4e4;
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regp->dither_regs[i + 3] = 0x44444444;
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}
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}
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} else {
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if (dev_priv->chipset != 0x11) {
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/* reset them */
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int i;
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for (i = 0; i < 3; i++) {
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regp->dither_regs[i] = savep->dither_regs[i];
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regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
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}
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}
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regp->dither = savep->dither;
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}
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regp->fp_margin_color = 0;
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}
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static void nv04_dfp_commit(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_encoder_helper_funcs *helper = encoder->helper_private;
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struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct dcb_entry *dcbe = nv_encoder->dcb;
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int head = nouveau_crtc(encoder->crtc)->index;
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NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
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drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
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nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
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if (dcbe->type == OUTPUT_TMDS)
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run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
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else if (dcbe->type == OUTPUT_LVDS)
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call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
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/* update fp_control state for any changes made by scripts,
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* so correct value is written at DPMS on */
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dev_priv->mode_reg.crtc_reg[head].fp_control =
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NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
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/* This could use refinement for flatpanels, but it should work this way */
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if (dev_priv->chipset < 0x44)
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
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else
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
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helper->dpms(encoder, DRM_MODE_DPMS_ON);
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NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
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drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
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nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
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}
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static inline bool is_powersaving_dpms(int mode)
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{
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return (mode != DRM_MODE_DPMS_ON);
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}
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static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_crtc *crtc = encoder->crtc;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
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if (nv_encoder->last_dpms == mode)
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return;
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nv_encoder->last_dpms = mode;
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NV_INFO(dev, "Setting dpms mode %d on lvds encoder (output %d)\n",
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mode, nv_encoder->dcb->index);
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if (was_powersaving && is_powersaving_dpms(mode))
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return;
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if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
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struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
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/* when removing an output, crtc may not be set, but PANEL_OFF
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* must still be run
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*/
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int head = crtc ? nouveau_crtc(crtc)->index :
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nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
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if (mode == DRM_MODE_DPMS_ON) {
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if (!nv_connector->native_mode) {
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NV_ERROR(dev, "Not turning on LVDS without native mode\n");
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return;
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}
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call_lvds_script(dev, nv_encoder->dcb, head,
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LVDS_PANEL_ON, nv_connector->native_mode->clock);
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} else
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/* pxclk of 0 is fine for PANEL_OFF, and for a
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* disconnected LVDS encoder there is no native_mode
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*/
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call_lvds_script(dev, nv_encoder->dcb, head,
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LVDS_PANEL_OFF, 0);
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}
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nv04_dfp_update_fp_control(encoder, mode);
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|
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if (mode == DRM_MODE_DPMS_ON)
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nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
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else {
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dev_priv->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
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dev_priv->mode_reg.sel_clk &= ~0xf0;
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}
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
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}
|
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static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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|
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if (nv_encoder->last_dpms == mode)
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return;
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nv_encoder->last_dpms = mode;
|
|
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NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n",
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mode, nv_encoder->dcb->index);
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|
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nv04_dfp_update_fp_control(encoder, mode);
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}
|
|
|
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static void nv04_dfp_save(struct drm_encoder *encoder)
|
|
{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
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struct drm_device *dev = encoder->dev;
|
|
|
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if (nv_two_heads(dev))
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nv_encoder->restore.head =
|
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nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
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}
|
|
|
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static void nv04_dfp_restore(struct drm_encoder *encoder)
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{
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
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struct drm_device *dev = encoder->dev;
|
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struct drm_nouveau_private *dev_priv = dev->dev_private;
|
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int head = nv_encoder->restore.head;
|
|
|
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if (nv_encoder->dcb->type == OUTPUT_LVDS) {
|
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struct drm_display_mode *native_mode = nouveau_encoder_connector_get(nv_encoder)->native_mode;
|
|
if (native_mode)
|
|
call_lvds_script(dev, nv_encoder->dcb, head, LVDS_PANEL_ON,
|
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native_mode->clock);
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else
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NV_ERROR(dev, "Not restoring LVDS without native mode\n");
|
|
|
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} else if (nv_encoder->dcb->type == OUTPUT_TMDS) {
|
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int clock = nouveau_hw_pllvals_to_clk
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(&dev_priv->saved_reg.crtc_reg[head].pllvals);
|
|
|
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run_tmds_table(dev, nv_encoder->dcb, head, clock);
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}
|
|
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nv_encoder->last_dpms = NV_DPMS_CLEARED;
|
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}
|
|
|
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static void nv04_dfp_destroy(struct drm_encoder *encoder)
|
|
{
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
|
|
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NV_DEBUG_KMS(encoder->dev, "\n");
|
|
|
|
drm_encoder_cleanup(encoder);
|
|
kfree(nv_encoder);
|
|
}
|
|
|
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static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
|
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.dpms = nv04_lvds_dpms,
|
|
.save = nv04_dfp_save,
|
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.restore = nv04_dfp_restore,
|
|
.mode_fixup = nv04_dfp_mode_fixup,
|
|
.prepare = nv04_dfp_prepare,
|
|
.commit = nv04_dfp_commit,
|
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.mode_set = nv04_dfp_mode_set,
|
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.detect = NULL,
|
|
};
|
|
|
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static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
|
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.dpms = nv04_tmds_dpms,
|
|
.save = nv04_dfp_save,
|
|
.restore = nv04_dfp_restore,
|
|
.mode_fixup = nv04_dfp_mode_fixup,
|
|
.prepare = nv04_dfp_prepare,
|
|
.commit = nv04_dfp_commit,
|
|
.mode_set = nv04_dfp_mode_set,
|
|
.detect = NULL,
|
|
};
|
|
|
|
static const struct drm_encoder_funcs nv04_dfp_funcs = {
|
|
.destroy = nv04_dfp_destroy,
|
|
};
|
|
|
|
int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry)
|
|
{
|
|
const struct drm_encoder_helper_funcs *helper;
|
|
struct drm_encoder *encoder;
|
|
struct nouveau_encoder *nv_encoder = NULL;
|
|
int type;
|
|
|
|
switch (entry->type) {
|
|
case OUTPUT_TMDS:
|
|
type = DRM_MODE_ENCODER_TMDS;
|
|
helper = &nv04_tmds_helper_funcs;
|
|
break;
|
|
case OUTPUT_LVDS:
|
|
type = DRM_MODE_ENCODER_LVDS;
|
|
helper = &nv04_lvds_helper_funcs;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
|
|
if (!nv_encoder)
|
|
return -ENOMEM;
|
|
|
|
encoder = to_drm_encoder(nv_encoder);
|
|
|
|
nv_encoder->dcb = entry;
|
|
nv_encoder->or = ffs(entry->or) - 1;
|
|
|
|
drm_encoder_init(dev, encoder, &nv04_dfp_funcs, type);
|
|
drm_encoder_helper_add(encoder, helper);
|
|
|
|
encoder->possible_crtcs = entry->heads;
|
|
encoder->possible_clones = 0;
|
|
|
|
return 0;
|
|
}
|