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e1dd23a001
Correct this. diff --git a/drivers/scsi/sata_sil.c b/drivers/scsi/sata_sil.c
503 lines
14 KiB
C
503 lines
14 KiB
C
/*
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* sata_sil.c - Silicon Image SATA
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003 Red Hat, Inc.
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* Copyright 2003 Benjamin Herrenschmidt
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*
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* The contents of this file are subject to the Open
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* Software License version 1.1 that can be found at
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* http://www.opensource.org/licenses/osl-1.1.txt and is included herein
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* by reference.
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the GNU General Public License version 2 (the "GPL") as distributed
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* in the kernel source COPYING file, in which case the provisions of
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* the GPL are applicable instead of the above. If you wish to allow
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* the use of your version of this file only under the terms of the
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* GPL and not to allow others to use your version of this file under
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* the OSL, indicate your decision by deleting the provisions above and
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* replace them with the notice and other provisions required by the GPL.
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* If you do not delete the provisions above, a recipient may use your
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* version of this file under either the OSL or the GPL.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_sil"
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#define DRV_VERSION "0.9"
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enum {
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sil_3112 = 0,
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sil_3114 = 1,
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SIL_FIFO_R0 = 0x40,
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SIL_FIFO_W0 = 0x41,
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SIL_FIFO_R1 = 0x44,
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SIL_FIFO_W1 = 0x45,
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SIL_FIFO_R2 = 0x240,
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SIL_FIFO_W2 = 0x241,
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SIL_FIFO_R3 = 0x244,
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SIL_FIFO_W3 = 0x245,
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SIL_SYSCFG = 0x48,
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SIL_MASK_IDE0_INT = (1 << 22),
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SIL_MASK_IDE1_INT = (1 << 23),
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SIL_MASK_IDE2_INT = (1 << 24),
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SIL_MASK_IDE3_INT = (1 << 25),
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SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
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SIL_MASK_4PORT = SIL_MASK_2PORT |
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SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
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SIL_IDE2_BMDMA = 0x200,
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SIL_INTR_STEERING = (1 << 1),
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SIL_QUIRK_MOD15WRITE = (1 << 0),
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SIL_QUIRK_UDMA5MAX = (1 << 1),
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};
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static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
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static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static void sil_post_set_mode (struct ata_port *ap);
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static struct pci_device_id sil_pci_tbl[] = {
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{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
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{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
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{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
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{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
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{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
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{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
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{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
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{ } /* terminate list */
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};
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/* TODO firmware versions should be added - eric */
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static const struct sil_drivelist {
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const char * product;
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unsigned int quirk;
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} sil_blacklist [] = {
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{ "ST320012AS", SIL_QUIRK_MOD15WRITE },
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{ "ST330013AS", SIL_QUIRK_MOD15WRITE },
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{ "ST340017AS", SIL_QUIRK_MOD15WRITE },
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{ "ST360015AS", SIL_QUIRK_MOD15WRITE },
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{ "ST380013AS", SIL_QUIRK_MOD15WRITE },
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{ "ST380023AS", SIL_QUIRK_MOD15WRITE },
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{ "ST3120023AS", SIL_QUIRK_MOD15WRITE },
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{ "ST3160023AS", SIL_QUIRK_MOD15WRITE },
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{ "ST3120026AS", SIL_QUIRK_MOD15WRITE },
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{ "ST3200822AS", SIL_QUIRK_MOD15WRITE },
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{ "ST340014ASL", SIL_QUIRK_MOD15WRITE },
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{ "ST360014ASL", SIL_QUIRK_MOD15WRITE },
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{ "ST380011ASL", SIL_QUIRK_MOD15WRITE },
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{ "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
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{ "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
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{ "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
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{ }
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};
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static struct pci_driver sil_pci_driver = {
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.name = DRV_NAME,
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.id_table = sil_pci_tbl,
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.probe = sil_init_one,
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.remove = ata_pci_remove_one,
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};
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static Scsi_Host_Template sil_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.eh_strategy_handler = ata_scsi_error,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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.ordered_flush = 1,
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};
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static struct ata_port_operations sil_ops = {
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.port_disable = ata_port_disable,
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.dev_config = sil_dev_config,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.phy_reset = sata_phy_reset,
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.post_set_mode = sil_post_set_mode,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.eng_timeout = ata_eng_timeout,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.scr_read = sil_scr_read,
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.scr_write = sil_scr_write,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop,
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};
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static struct ata_port_info sil_port_info[] = {
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/* sil_3112 */
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{
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.sht = &sil_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_SRST | ATA_FLAG_MMIO,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x3f, /* udma0-5 */
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.port_ops = &sil_ops,
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}, /* sil_3114 */
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{
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.sht = &sil_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_SRST | ATA_FLAG_MMIO,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x3f, /* udma0-5 */
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.port_ops = &sil_ops,
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},
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};
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/* per-port register offsets */
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/* TODO: we can probably calculate rather than use a table */
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static const struct {
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unsigned long tf; /* ATA taskfile register block */
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unsigned long ctl; /* ATA control/altstatus register block */
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unsigned long bmdma; /* DMA register block */
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unsigned long scr; /* SATA control register block */
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unsigned long sien; /* SATA Interrupt Enable register */
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unsigned long xfer_mode;/* data transfer mode register */
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} sil_port[] = {
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/* port 0 ... */
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{ 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
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{ 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
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{ 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
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{ 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
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/* ... port 3 */
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};
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MODULE_AUTHOR("Jeff Garzik");
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MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
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{
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u8 cache_line = 0;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
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return cache_line;
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}
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static void sil_post_set_mode (struct ata_port *ap)
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{
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struct ata_host_set *host_set = ap->host_set;
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struct ata_device *dev;
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void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
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u32 tmp, dev_mode[2];
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unsigned int i;
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for (i = 0; i < 2; i++) {
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dev = &ap->device[i];
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if (!ata_dev_present(dev))
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dev_mode[i] = 0; /* PIO0/1/2 */
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else if (dev->flags & ATA_DFLAG_PIO)
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dev_mode[i] = 1; /* PIO3/4 */
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else
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dev_mode[i] = 3; /* UDMA */
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/* value 2 indicates MDMA */
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}
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tmp = readl(addr);
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tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
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tmp |= dev_mode[0];
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tmp |= (dev_mode[1] << 4);
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writel(tmp, addr);
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readl(addr); /* flush */
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}
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static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
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{
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unsigned long offset = ap->ioaddr.scr_addr;
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switch (sc_reg) {
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case SCR_STATUS:
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return offset + 4;
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case SCR_ERROR:
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return offset + 8;
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case SCR_CONTROL:
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return offset;
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default:
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/* do nothing */
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break;
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}
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return 0;
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}
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static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
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{
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void *mmio = (void *) sil_scr_addr(ap, sc_reg);
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if (mmio)
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return readl(mmio);
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return 0xffffffffU;
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}
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static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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{
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void *mmio = (void *) sil_scr_addr(ap, sc_reg);
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if (mmio)
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writel(val, mmio);
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}
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/**
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* sil_dev_config - Apply device/host-specific errata fixups
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* @ap: Port containing device to be examined
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* @dev: Device to be examined
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*
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* After the IDENTIFY [PACKET] DEVICE step is complete, and a
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* device is known to be present, this function is called.
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* We apply two errata fixups which are specific to Silicon Image,
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* a Seagate and a Maxtor fixup.
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*
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* For certain Seagate devices, we must limit the maximum sectors
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* to under 8K.
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*
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* For certain Maxtor devices, we must not program the drive
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* beyond udma5.
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*
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* Both fixups are unfairly pessimistic. As soon as I get more
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* information on these errata, I will create a more exhaustive
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* list, and apply the fixups to only the specific
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* devices/hosts/firmwares that need it.
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*
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* 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
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* The Maxtor quirk is in the blacklist, but I'm keeping the original
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* pessimistic fix for the following reasons...
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* - There seems to be less info on it, only one device gleaned off the
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* Windows driver, maybe only one is affected. More info would be greatly
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* appreciated.
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* - But then again UDMA5 is hardly anything to complain about
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*/
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static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
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{
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unsigned int n, quirks = 0;
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unsigned char model_num[40];
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const char *s;
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unsigned int len;
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ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
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sizeof(model_num));
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s = &model_num[0];
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len = strnlen(s, sizeof(model_num));
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/* ATAPI specifies that empty space is blank-filled; remove blanks */
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while ((len > 0) && (s[len - 1] == ' '))
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len--;
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for (n = 0; sil_blacklist[n].product; n++)
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if (!memcmp(sil_blacklist[n].product, s,
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strlen(sil_blacklist[n].product))) {
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quirks = sil_blacklist[n].quirk;
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break;
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}
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/* limit requests to 15 sectors */
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if (quirks & SIL_QUIRK_MOD15WRITE) {
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printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
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ap->id, dev->devno);
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ap->host->max_sectors = 15;
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ap->host->hostt->max_sectors = 15;
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dev->flags |= ATA_DFLAG_LOCK_SECTORS;
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return;
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}
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/* limit to udma5 */
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if (quirks & SIL_QUIRK_UDMA5MAX) {
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printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
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ap->id, dev->devno, s);
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ap->udma_mask &= ATA_UDMA5;
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return;
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}
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}
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static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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struct ata_probe_ent *probe_ent = NULL;
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unsigned long base;
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void *mmio_base;
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int rc;
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unsigned int i;
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int pci_dev_busy = 0;
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u32 tmp, irq_mask;
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u8 cls;
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if (!printed_version++)
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printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
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/*
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* If this driver happens to only be useful on Apple's K2, then
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* we should check that here as it has a normal Serverworks ID
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*/
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rc = pci_enable_device(pdev);
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if (rc)
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return rc;
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rc = pci_request_regions(pdev, DRV_NAME);
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if (rc) {
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pci_dev_busy = 1;
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goto err_out;
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}
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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goto err_out_regions;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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goto err_out_regions;
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probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
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if (probe_ent == NULL) {
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rc = -ENOMEM;
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goto err_out_regions;
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}
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memset(probe_ent, 0, sizeof(*probe_ent));
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INIT_LIST_HEAD(&probe_ent->node);
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probe_ent->dev = pci_dev_to_dev(pdev);
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probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
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probe_ent->sht = sil_port_info[ent->driver_data].sht;
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probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
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probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
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probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
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probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
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probe_ent->irq = pdev->irq;
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probe_ent->irq_flags = SA_SHIRQ;
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probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
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mmio_base = ioremap(pci_resource_start(pdev, 5),
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pci_resource_len(pdev, 5));
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if (mmio_base == NULL) {
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rc = -ENOMEM;
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goto err_out_free_ent;
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}
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probe_ent->mmio_base = mmio_base;
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base = (unsigned long) mmio_base;
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for (i = 0; i < probe_ent->n_ports; i++) {
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probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
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probe_ent->port[i].altstatus_addr =
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probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
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probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
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probe_ent->port[i].scr_addr = base + sil_port[i].scr;
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ata_std_ports(&probe_ent->port[i]);
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}
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/* Initialize FIFO PCI bus arbitration */
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cls = sil_get_device_cache_line(pdev);
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if (cls) {
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cls >>= 3;
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cls++; /* cls = (line_size/8)+1 */
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writeb(cls, mmio_base + SIL_FIFO_R0);
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writeb(cls, mmio_base + SIL_FIFO_W0);
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writeb(cls, mmio_base + SIL_FIFO_R1);
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writeb(cls, mmio_base + SIL_FIFO_W1);
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if (ent->driver_data == sil_3114) {
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writeb(cls, mmio_base + SIL_FIFO_R2);
|
|
writeb(cls, mmio_base + SIL_FIFO_W2);
|
|
writeb(cls, mmio_base + SIL_FIFO_R3);
|
|
writeb(cls, mmio_base + SIL_FIFO_W3);
|
|
}
|
|
} else
|
|
printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n",
|
|
pci_name(pdev));
|
|
|
|
if (ent->driver_data == sil_3114) {
|
|
irq_mask = SIL_MASK_4PORT;
|
|
|
|
/* flip the magic "make 4 ports work" bit */
|
|
tmp = readl(mmio_base + SIL_IDE2_BMDMA);
|
|
if ((tmp & SIL_INTR_STEERING) == 0)
|
|
writel(tmp | SIL_INTR_STEERING,
|
|
mmio_base + SIL_IDE2_BMDMA);
|
|
|
|
} else {
|
|
irq_mask = SIL_MASK_2PORT;
|
|
}
|
|
|
|
/* make sure IDE0/1/2/3 interrupts are not masked */
|
|
tmp = readl(mmio_base + SIL_SYSCFG);
|
|
if (tmp & irq_mask) {
|
|
tmp &= ~irq_mask;
|
|
writel(tmp, mmio_base + SIL_SYSCFG);
|
|
readl(mmio_base + SIL_SYSCFG); /* flush */
|
|
}
|
|
|
|
/* mask all SATA phy-related interrupts */
|
|
/* TODO: unmask bit 6 (SError N bit) for hotplug */
|
|
for (i = 0; i < probe_ent->n_ports; i++)
|
|
writel(0, mmio_base + sil_port[i].sien);
|
|
|
|
pci_set_master(pdev);
|
|
|
|
/* FIXME: check ata_device_add return value */
|
|
ata_device_add(probe_ent);
|
|
kfree(probe_ent);
|
|
|
|
return 0;
|
|
|
|
err_out_free_ent:
|
|
kfree(probe_ent);
|
|
err_out_regions:
|
|
pci_release_regions(pdev);
|
|
err_out:
|
|
if (!pci_dev_busy)
|
|
pci_disable_device(pdev);
|
|
return rc;
|
|
}
|
|
|
|
static int __init sil_init(void)
|
|
{
|
|
return pci_module_init(&sil_pci_driver);
|
|
}
|
|
|
|
static void __exit sil_exit(void)
|
|
{
|
|
pci_unregister_driver(&sil_pci_driver);
|
|
}
|
|
|
|
|
|
module_init(sil_init);
|
|
module_exit(sil_exit);
|