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d51d0af43b
A few GICv2 low-level function are actually very useful to GICv3, and it makes some sense to share them across the two drivers. They end-up in their own file, with an additional parameter used to ensure an optional synchronization (unused on GICv2). Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
116 lines
3.1 KiB
C
116 lines
3.1 KiB
C
/*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include "irq-gic-common.h"
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void gic_configure_irq(unsigned int irq, unsigned int type,
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void __iomem *base, void (*sync_access)(void))
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{
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u32 enablemask = 1 << (irq % 32);
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u32 enableoff = (irq / 32) * 4;
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u32 confmask = 0x2 << ((irq % 16) * 2);
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u32 confoff = (irq / 16) * 4;
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bool enabled = false;
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u32 val;
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/*
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* Read current configuration register, and insert the config
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* for "irq", depending on "type".
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*/
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val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
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if (type == IRQ_TYPE_LEVEL_HIGH)
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val &= ~confmask;
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else if (type == IRQ_TYPE_EDGE_RISING)
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val |= confmask;
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/*
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* As recommended by the spec, disable the interrupt before changing
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* the configuration
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*/
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if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
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if (sync_access)
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sync_access();
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enabled = true;
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}
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/*
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* Write back the new configuration, and possibly re-enable
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* the interrupt.
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*/
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writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
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if (enabled)
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
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if (sync_access)
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sync_access();
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}
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void __init gic_dist_config(void __iomem *base, int gic_irqs,
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void (*sync_access)(void))
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{
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unsigned int i;
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < gic_irqs; i += 16)
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writel_relaxed(0, base + GIC_DIST_CONFIG + i / 4);
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/*
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* Set priority on all global interrupts.
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*/
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for (i = 32; i < gic_irqs; i += 4)
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writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i);
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/*
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* Disable all interrupts. Leave the PPI and SGIs alone
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* as they are enabled by redistributor registers.
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*/
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for (i = 32; i < gic_irqs; i += 32)
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writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i / 8);
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if (sync_access)
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sync_access();
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}
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void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
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{
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int i;
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/*
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* Deal with the banked PPI and SGI interrupts - disable all
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* PPI interrupts, ensure all SGI interrupts are enabled.
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*/
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writel_relaxed(0xffff0000, base + GIC_DIST_ENABLE_CLEAR);
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writel_relaxed(0x0000ffff, base + GIC_DIST_ENABLE_SET);
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/*
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < 32; i += 4)
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writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
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if (sync_access)
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sync_access();
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}
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