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37987ba4d1
Instead of using IO_ADDR_W and IO_ADDR_R use an own pointer to the NAND controller memory area. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
249 lines
6.6 KiB
C
249 lines
6.6 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright © 2012 John Crispin <blogic@openwrt.org>
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* Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
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*/
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#include <linux/mtd/nand.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
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#include <lantiq_soc.h>
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/* nand registers */
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#define EBU_ADDSEL1 0x24
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#define EBU_NAND_CON 0xB0
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#define EBU_NAND_WAIT 0xB4
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#define NAND_WAIT_RD BIT(0) /* NAND flash status output */
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#define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
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#define EBU_NAND_ECC0 0xB8
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#define EBU_NAND_ECC_AC 0xBC
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/*
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* nand commands
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* The pins of the NAND chip are selected based on the address bits of the
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* "register" read and write. There are no special registers, but an
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* address range and the lower address bits are used to activate the
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* correct line. For example when the bit (1 << 2) is set in the address
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* the ALE pin will be activated.
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*/
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#define NAND_CMD_ALE BIT(2) /* address latch enable */
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#define NAND_CMD_CLE BIT(3) /* command latch enable */
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#define NAND_CMD_CS BIT(4) /* chip select */
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#define NAND_CMD_SE BIT(5) /* spare area access latch */
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#define NAND_CMD_WP BIT(6) /* write protect */
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#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
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#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
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#define NAND_WRITE_DATA (NAND_CMD_CS)
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#define NAND_READ_DATA (NAND_CMD_CS)
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/* we need to tel the ebu which addr we mapped the nand to */
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#define ADDSEL1_MASK(x) (x << 4)
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#define ADDSEL1_REGEN 1
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/* we need to tell the EBU that we have nand attached and set it up properly */
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#define BUSCON1_SETUP (1 << 22)
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#define BUSCON1_BCGEN_RES (0x3 << 12)
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#define BUSCON1_WAITWRC2 (2 << 8)
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#define BUSCON1_WAITRDC2 (2 << 6)
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#define BUSCON1_HOLDC1 (1 << 4)
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#define BUSCON1_RECOVC1 (1 << 2)
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#define BUSCON1_CMULT4 1
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#define NAND_CON_CE (1 << 20)
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#define NAND_CON_OUT_CS1 (1 << 10)
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#define NAND_CON_IN_CS1 (1 << 8)
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#define NAND_CON_PRE_P (1 << 7)
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#define NAND_CON_WP_P (1 << 6)
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#define NAND_CON_SE_P (1 << 5)
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#define NAND_CON_CS_P (1 << 4)
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#define NAND_CON_CSMUX (1 << 1)
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#define NAND_CON_NANDM 1
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struct xway_nand_data {
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struct nand_chip chip;
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unsigned long csflags;
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void __iomem *nandaddr;
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};
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static u8 xway_readb(struct mtd_info *mtd, int op)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct xway_nand_data *data = nand_get_controller_data(chip);
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return readb(data->nandaddr + op);
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}
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static void xway_writeb(struct mtd_info *mtd, int op, u8 value)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct xway_nand_data *data = nand_get_controller_data(chip);
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writeb(value, data->nandaddr + op);
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}
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static void xway_select_chip(struct mtd_info *mtd, int select)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct xway_nand_data *data = nand_get_controller_data(chip);
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switch (select) {
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case -1:
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ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
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ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
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spin_unlock_irqrestore(&ebu_lock, data->csflags);
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break;
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case 0:
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spin_lock_irqsave(&ebu_lock, data->csflags);
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ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
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ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
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break;
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default:
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BUG();
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}
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}
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static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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xway_writeb(mtd, NAND_WRITE_CMD, cmd);
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else if (ctrl & NAND_ALE)
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xway_writeb(mtd, NAND_WRITE_ADDR, cmd);
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while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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;
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}
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static int xway_dev_ready(struct mtd_info *mtd)
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{
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return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
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}
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static unsigned char xway_read_byte(struct mtd_info *mtd)
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{
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return xway_readb(mtd, NAND_READ_DATA);
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}
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static void xway_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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buf[i] = xway_readb(mtd, NAND_WRITE_DATA);
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}
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static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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xway_writeb(mtd, NAND_WRITE_DATA, buf[i]);
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}
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/*
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* Probe for the NAND device.
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*/
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static int xway_nand_probe(struct platform_device *pdev)
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{
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struct xway_nand_data *data;
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struct mtd_info *mtd;
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struct resource *res;
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int err;
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u32 cs;
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u32 cs_flag = 0;
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/* Allocate memory for the device structure (and zero it) */
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data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
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GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->nandaddr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->nandaddr))
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return PTR_ERR(data->nandaddr);
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nand_set_flash_node(&data->chip, pdev->dev.of_node);
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mtd = nand_to_mtd(&data->chip);
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mtd->dev.parent = &pdev->dev;
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data->chip.cmd_ctrl = xway_cmd_ctrl;
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data->chip.dev_ready = xway_dev_ready;
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data->chip.select_chip = xway_select_chip;
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data->chip.write_buf = xway_write_buf;
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data->chip.read_buf = xway_read_buf;
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data->chip.read_byte = xway_read_byte;
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data->chip.chip_delay = 30;
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data->chip.ecc.mode = NAND_ECC_SOFT;
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data->chip.ecc.algo = NAND_ECC_HAMMING;
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platform_set_drvdata(pdev, data);
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nand_set_controller_data(&data->chip, data);
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/* load our CS from the DT. Either we find a valid 1 or default to 0 */
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err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs);
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if (!err && cs == 1)
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cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
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/* setup the EBU to run in NAND mode on our base addr */
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ltq_ebu_w32(CPHYSADDR(data->nandaddr)
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| ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
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ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
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| BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
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| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
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ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
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| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
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| cs_flag, EBU_NAND_CON);
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/* Scan to find existence of the device */
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err = nand_scan(mtd, 1);
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if (err)
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return err;
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err = mtd_device_register(mtd, NULL, 0);
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if (err)
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nand_release(mtd);
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return err;
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}
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/*
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* Remove a NAND device.
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*/
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static int xway_nand_remove(struct platform_device *pdev)
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{
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struct xway_nand_data *data = platform_get_drvdata(pdev);
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nand_release(nand_to_mtd(&data->chip));
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return 0;
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}
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static const struct of_device_id xway_nand_match[] = {
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{ .compatible = "lantiq,nand-xway" },
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{},
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};
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MODULE_DEVICE_TABLE(of, xway_nand_match);
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static struct platform_driver xway_nand_driver = {
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.probe = xway_nand_probe,
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.remove = xway_nand_remove,
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.driver = {
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.name = "lantiq,nand-xway",
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.of_match_table = xway_nand_match,
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},
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};
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module_platform_driver(xway_nand_driver);
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MODULE_LICENSE("GPL");
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