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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
135 lines
4.5 KiB
Plaintext
135 lines
4.5 KiB
Plaintext
=====================================
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FUJITSU FR-V KERNEL ATOMIC OPERATIONS
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=====================================
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On the FR-V CPUs, there is only one atomic Read-Modify-Write operation: the SWAP/SWAPI
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instruction. Unfortunately, this alone can't be used to implement the following operations:
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(*) Atomic add to memory
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(*) Atomic subtract from memory
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(*) Atomic bit modification (set, clear or invert)
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(*) Atomic compare and exchange
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On such CPUs, the standard way of emulating such operations in uniprocessor mode is to disable
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interrupts, but on the FR-V CPUs, modifying the PSR takes a lot of clock cycles, and it has to be
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done twice. This means the CPU runs for a relatively long time with interrupts disabled,
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potentially having a great effect on interrupt latency.
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=============
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NEW ALGORITHM
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=============
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To get around this, the following algorithm has been implemented. It operates in a way similar to
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the LL/SC instruction pairs supported on a number of platforms.
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(*) The CCCR.CC3 register is reserved within the kernel to act as an atomic modify abort flag.
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(*) In the exception prologues run on kernel->kernel entry, CCCR.CC3 is set to 0 (Undefined
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state).
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(*) All atomic operations can then be broken down into the following algorithm:
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(1) Set ICC3.Z to true and set CC3 to True (ORCC/CKEQ/ORCR).
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(2) Load the value currently in the memory to be modified into a register.
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(3) Make changes to the value.
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(4) If CC3 is still True, simultaneously and atomically (by VLIW packing):
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(a) Store the modified value back to memory.
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(b) Set ICC3.Z to false (CORCC on GR29 is sufficient for this - GR29 holds the current
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task pointer in the kernel, and so is guaranteed to be non-zero).
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(5) If ICC3.Z is still true, go back to step (1).
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This works in a non-SMP environment because any interrupt or other exception that happens between
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steps (1) and (4) will set CC3 to the Undefined, thus aborting the store in (4a), and causing the
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condition in ICC3 to remain with the Z flag set, thus causing step (5) to loop back to step (1).
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This algorithm suffers from two problems:
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(1) The condition CCCR.CC3 is cleared unconditionally by an exception, irrespective of whether or
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not any changes were made to the target memory location during that exception.
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(2) The branch from step (5) back to step (1) may have to happen more than once until the store
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manages to take place. In theory, this loop could cycle forever because there are too many
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interrupts coming in, but it's unlikely.
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=======
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EXAMPLE
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=======
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Taking an example from include/asm-frv/atomic.h:
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long val;
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asm("0: \n"
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It starts by setting ICC3.Z to true for later use, and also transforming that into CC3 being in the
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True state.
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" orcc gr0,gr0,gr0,icc3 \n" <-- (1)
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" ckeq icc3,cc7 \n" <-- (1)
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Then it does the load. Note that the final phase of step (1) is done at the same time as the
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load. The VLIW packing ensures they are done simultaneously. The ".p" on the load must not be
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removed without swapping the order of these two instructions.
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" ld.p %M0,%1 \n" <-- (2)
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" orcr cc7,cc7,cc3 \n" <-- (1)
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Then the proposed modification is generated. Note that the old value can be retained if required
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(such as in test_and_set_bit()).
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" add%I2 %1,%2,%1 \n" <-- (3)
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Then it attempts to store the value back, contingent on no exception having cleared CC3 since it
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was set to True.
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" cst.p %1,%M0 ,cc3,#1 \n" <-- (4a)
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It simultaneously records the success or failure of the store in ICC3.Z.
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" <-- (4b)
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Such that the branch can then be taken if the operation was aborted.
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" beq icc3,#0,0b \n" <-- (5)
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: "+U"(v->counter), "=&r"(val)
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: "NPr"(i)
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: "memory", "cc7", "cc3", "icc3"
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);
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return val;
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}
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=============
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CONFIGURATION
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=============
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The atomic ops implementation can be made inline or out-of-line by changing the
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CONFIG_FRV_OUTOFLINE_ATOMIC_OPS configuration variable. Making it out-of-line has a number of
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advantages:
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- The resulting kernel image may be smaller
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- Debugging is easier as atomic ops can just be stepped over and they can be breakpointed
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Keeping it inline also has a number of advantages:
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- The resulting kernel may be Faster
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- no out-of-line function calls need to be made
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- the compiler doesn't have half its registers clobbered by making a call
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The out-of-line implementations live in arch/frv/lib/atomic-ops.S.
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