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On Intel platforms machine check exceptions are always broadcast to all CPUs. This patch makes the machine check handler synchronize all these machine checks, elect a Monarch to handle the event and collect the worst event from all CPUs and then process it first. This has some advantages: - When there is a truly data corrupting error the system panics as quickly as possible. This improves containment of corrupted data and makes sure the corrupted data never hits stable storage. - The panics are synchronized and do not reenter the panic code on multiple CPUs (which currently does not handle this well). - All the errors are reported. Currently it often happens that another CPU happens to do the panic first, but reports useless information (empty machine check) because the real error happened on another CPU which came in later. This is a big advantage on Nehalem where the 8 threads per CPU lead to often the wrong CPU winning the race and dumping useless information on a machine check. The problem also occurs in a less severe form on older CPUs. - The system can detect when no CPUs detected a machine check and shut down the system. This can happen when one CPU is so badly hung that that it cannot process a machine check anymore or when some external agent wants to stop the system by asserting the machine check pin. This follows Intel hardware recommendations. - This matches the recommended error model by the CPU designers. - The events can be output in true severity order - When a panic happens on another CPU it makes sure to be actually be able to process the stop IPI by enabling interrupts. The code is extremly careful to handle timeouts while waiting for other CPUs. It can't rely on the normal timing mechanisms (jiffies, ktime_get) because of its asynchronous/lockless nature, so it uses own timeouts using ndelay() and a "SPINUNIT" The timeout is configurable. By default it waits for upto one second for the other CPUs. This can be also disabled. From some informal testing AMD systems do not see to broadcast machine checks, so right now it's always disabled by default on non Intel CPUs or also on very old Intel systems. Includes fixes from Ying Huang Fixed a "ecception" in a comment (H.Seto) Moved global_nwo reset later based on suggestion from H.Seto v2: Avoid duplicate messages [ Impact: feature, fixes long standing problems. ] Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
84 lines
3.2 KiB
Plaintext
84 lines
3.2 KiB
Plaintext
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Configurable sysfs parameters for the x86-64 machine check code.
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Machine checks report internal hardware error conditions detected
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by the CPU. Uncorrected errors typically cause a machine check
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(often with panic), corrected ones cause a machine check log entry.
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Machine checks are organized in banks (normally associated with
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a hardware subsystem) and subevents in a bank. The exact meaning
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of the banks and subevent is CPU specific.
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mcelog knows how to decode them.
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When you see the "Machine check errors logged" message in the system
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log then mcelog should run to collect and decode machine check entries
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from /dev/mcelog. Normally mcelog should be run regularly from a cronjob.
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Each CPU has a directory in /sys/devices/system/machinecheck/machinecheckN
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(N = CPU number)
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The directory contains some configurable entries:
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Entries:
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bankNctl
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(N bank number)
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64bit Hex bitmask enabling/disabling specific subevents for bank N
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When a bit in the bitmask is zero then the respective
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subevent will not be reported.
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By default all events are enabled.
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Note that BIOS maintain another mask to disable specific events
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per bank. This is not visible here
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The following entries appear for each CPU, but they are truly shared
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between all CPUs.
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check_interval
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How often to poll for corrected machine check errors, in seconds
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(Note output is hexademical). Default 5 minutes. When the poller
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finds MCEs it triggers an exponential speedup (poll more often) on
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the polling interval. When the poller stops finding MCEs, it
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triggers an exponential backoff (poll less often) on the polling
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interval. The check_interval variable is both the initial and
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maximum polling interval. 0 means no polling for corrected machine
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check errors (but some corrected errors might be still reported
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in other ways)
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tolerant
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Tolerance level. When a machine check exception occurs for a non
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corrected machine check the kernel can take different actions.
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Since machine check exceptions can happen any time it is sometimes
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risky for the kernel to kill a process because it defies
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normal kernel locking rules. The tolerance level configures
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how hard the kernel tries to recover even at some risk of
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deadlock. Higher tolerant values trade potentially better uptime
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with the risk of a crash or even corruption (for tolerant >= 3).
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0: always panic on uncorrected errors, log corrected errors
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1: panic or SIGBUS on uncorrected errors, log corrected errors
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2: SIGBUS or log uncorrected errors, log corrected errors
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3: never panic or SIGBUS, log all errors (for testing only)
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Default: 1
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Note this only makes a difference if the CPU allows recovery
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from a machine check exception. Current x86 CPUs generally do not.
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trigger
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Program to run when a machine check event is detected.
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This is an alternative to running mcelog regularly from cron
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and allows to detect events faster.
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monarch_timeout
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How long to wait for the other CPUs to machine check too on a
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exception. 0 to disable waiting for other CPUs.
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Unit: us
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TBD document entries for AMD threshold interrupt configuration
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For more details about the x86 machine check architecture
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see the Intel and AMD architecture manuals from their developer websites.
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For more details about the architecture see
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see http://one.firstfloor.org/~andi/mce.pdf
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