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2c578a1be8
R-Car H2 has many DMACs (ex SYS-DMAC, 2D-DMAC, Audio-DMAC, USB-DMAC etc) and, these DMAEngine needs DMA slave IDs to use it. This patch adds new DMA slave ID list for r8a7790. There, common part has RCAR_DMA_xxx prefix, and Audio DMAC part has AUDIO_DMAC_SLAVE_xxx prefix. Audio DMAC can be controlled via sh-dma-engine Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
334 lines
10 KiB
C
334 lines
10 KiB
C
/*
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* r8a7790 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_dma.h>
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#include <linux/sh_timer.h>
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#include <mach/common.h>
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#include <mach/dma-register.h>
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#include <mach/irqs.h>
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#include <mach/r8a7790.h>
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#include <asm/mach/arch.h>
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/* Audio-DMAC */
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#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
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{ \
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.slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
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.addr = _addr + 0x8, \
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.chcr = CHCR_TX(XMIT_SZ_32BIT), \
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.mid_rid = t, \
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}, { \
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.slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
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.addr = _addr + 0xc, \
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.chcr = CHCR_RX(XMIT_SZ_32BIT), \
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.mid_rid = r, \
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}
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static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
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AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
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AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
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AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
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AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
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AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
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AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
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AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
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AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
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AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
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AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
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};
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#define DMAE_CHANNEL(a, b) \
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{ \
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.offset = (a) - 0x20, \
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.dmars = (a) - 0x20 + 0x40, \
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.chclr_bit = (b), \
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.chclr_offset = 0x80 - 0x20, \
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}
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static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
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DMAE_CHANNEL(0x8000, 0),
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DMAE_CHANNEL(0x8080, 1),
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DMAE_CHANNEL(0x8100, 2),
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DMAE_CHANNEL(0x8180, 3),
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DMAE_CHANNEL(0x8200, 4),
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DMAE_CHANNEL(0x8280, 5),
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DMAE_CHANNEL(0x8300, 6),
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DMAE_CHANNEL(0x8380, 7),
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DMAE_CHANNEL(0x8400, 8),
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DMAE_CHANNEL(0x8480, 9),
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DMAE_CHANNEL(0x8500, 10),
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DMAE_CHANNEL(0x8580, 11),
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DMAE_CHANNEL(0x8600, 12),
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};
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static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
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.slave = r8a7790_audio_dmac_slaves,
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.slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
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.channel = r8a7790_audio_dmac_channels,
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.channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
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.ts_low_shift = TS_LOW_SHIFT,
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.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
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.ts_high_shift = TS_HI_SHIFT,
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.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
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.ts_shift = dma_ts_shift,
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.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
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.dmaor_init = DMAOR_DME,
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.chclr_present = 1,
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.chclr_bitwise = 1,
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};
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static struct resource r8a7790_audio_dmac_resources[] = {
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/* Channel registers and DMAOR for low */
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DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
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DEFINE_RES_IRQ(gic_spi(346)),
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DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
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/* Channel registers and DMAOR for hi */
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DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
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DEFINE_RES_IRQ(gic_spi(347)),
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DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
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};
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#define r8a7790_register_audio_dmac(id) \
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platform_device_register_resndata( \
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&platform_bus, "sh-dma-engine", id, \
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&r8a7790_audio_dmac_resources[id * 3], 3, \
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&r8a7790_audio_dmac_platform_data, \
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sizeof(r8a7790_audio_dmac_platform_data))
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static const struct resource pfc_resources[] __initconst = {
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DEFINE_RES_MEM(0xe6060000, 0x250),
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};
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#define r8a7790_register_pfc() \
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platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
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ARRAY_SIZE(pfc_resources))
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#define R8A7790_GPIO(idx) \
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static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
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DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
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DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
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}; \
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\
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static const struct gpio_rcar_config \
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r8a7790_gpio##idx##_platform_data __initconst = { \
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.gpio_base = 32 * (idx), \
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.irq_base = 0, \
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.number_of_pins = 32, \
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.pctl_name = "pfc-r8a7790", \
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.has_both_edge_trigger = 1, \
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}; \
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R8A7790_GPIO(0);
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R8A7790_GPIO(1);
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R8A7790_GPIO(2);
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R8A7790_GPIO(3);
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R8A7790_GPIO(4);
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R8A7790_GPIO(5);
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#define r8a7790_register_gpio(idx) \
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platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
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r8a7790_gpio##idx##_resources, \
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ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
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&r8a7790_gpio##idx##_platform_data, \
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sizeof(r8a7790_gpio##idx##_platform_data))
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static struct resource i2c_resources[] __initdata = {
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/* I2C0 */
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DEFINE_RES_MEM(0xE6508000, 0x40),
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DEFINE_RES_IRQ(gic_spi(287)),
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/* I2C1 */
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DEFINE_RES_MEM(0xE6518000, 0x40),
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DEFINE_RES_IRQ(gic_spi(288)),
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/* I2C2 */
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DEFINE_RES_MEM(0xE6530000, 0x40),
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DEFINE_RES_IRQ(gic_spi(286)),
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/* I2C3 */
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DEFINE_RES_MEM(0xE6540000, 0x40),
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DEFINE_RES_IRQ(gic_spi(290)),
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};
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#define r8a7790_register_i2c(idx) \
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platform_device_register_simple( \
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"i2c-rcar_gen2", idx, \
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i2c_resources + (2 * idx), 2); \
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void __init r8a7790_pinmux_init(void)
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{
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r8a7790_register_pfc();
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r8a7790_register_gpio(0);
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r8a7790_register_gpio(1);
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r8a7790_register_gpio(2);
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r8a7790_register_gpio(3);
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r8a7790_register_gpio(4);
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r8a7790_register_gpio(5);
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r8a7790_register_i2c(0);
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r8a7790_register_i2c(1);
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r8a7790_register_i2c(2);
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r8a7790_register_i2c(3);
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r8a7790_register_audio_dmac(0);
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r8a7790_register_audio_dmac(1);
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}
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#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
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static struct plat_sci_port scif##index##_platform_data = { \
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.type = scif_type, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scscr = _scscr, \
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}; \
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\
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static struct resource scif##index##_resources[] = { \
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DEFINE_RES_MEM(baseaddr, 0x100), \
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DEFINE_RES_IRQ(irq), \
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}
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#define R8A7790_SCIF(index, baseaddr, irq) \
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__R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
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index, baseaddr, irq)
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#define R8A7790_SCIFA(index, baseaddr, irq) \
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__R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
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index, baseaddr, irq)
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#define R8A7790_SCIFB(index, baseaddr, irq) \
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__R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
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index, baseaddr, irq)
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#define R8A7790_HSCIF(index, baseaddr, irq) \
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__R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
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index, baseaddr, irq)
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R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
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R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
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R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
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R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
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R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
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R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
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R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
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R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
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R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
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R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
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#define r8a7790_register_scif(index) \
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platform_device_register_resndata(&platform_bus, "sh-sci", index, \
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scif##index##_resources, \
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ARRAY_SIZE(scif##index##_resources), \
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&scif##index##_platform_data, \
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sizeof(scif##index##_platform_data))
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static const struct renesas_irqc_config irqc0_data __initconst = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
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};
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static const struct resource irqc0_resources[] __initconst = {
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DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
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DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
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};
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#define r8a7790_register_irqc(idx) \
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platform_device_register_resndata(&platform_bus, "renesas_irqc", \
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idx, irqc##idx##_resources, \
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ARRAY_SIZE(irqc##idx##_resources), \
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&irqc##idx##_data, \
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sizeof(struct renesas_irqc_config))
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static const struct resource thermal_resources[] __initconst = {
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DEFINE_RES_MEM(0xe61f0000, 0x14),
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DEFINE_RES_MEM(0xe61f0100, 0x38),
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DEFINE_RES_IRQ(gic_spi(69)),
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};
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#define r8a7790_register_thermal() \
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platform_device_register_simple("rcar_thermal", -1, \
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thermal_resources, \
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ARRAY_SIZE(thermal_resources))
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static const struct sh_timer_config cmt00_platform_data __initconst = {
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.name = "CMT00",
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.timer_bit = 0,
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.clockevent_rating = 80,
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};
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static const struct resource cmt00_resources[] __initconst = {
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DEFINE_RES_MEM(0xffca0510, 0x0c),
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DEFINE_RES_MEM(0xffca0500, 0x04),
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DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
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};
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#define r8a7790_register_cmt(idx) \
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platform_device_register_resndata(&platform_bus, "sh_cmt", \
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idx, cmt##idx##_resources, \
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ARRAY_SIZE(cmt##idx##_resources), \
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&cmt##idx##_platform_data, \
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sizeof(struct sh_timer_config))
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void __init r8a7790_add_dt_devices(void)
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{
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r8a7790_register_scif(0);
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r8a7790_register_scif(1);
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r8a7790_register_scif(2);
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r8a7790_register_scif(3);
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r8a7790_register_scif(4);
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r8a7790_register_scif(5);
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r8a7790_register_scif(6);
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r8a7790_register_scif(7);
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r8a7790_register_scif(8);
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r8a7790_register_scif(9);
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r8a7790_register_cmt(00);
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}
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void __init r8a7790_add_standard_devices(void)
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{
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r8a7790_add_dt_devices();
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r8a7790_register_irqc(0);
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r8a7790_register_thermal();
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}
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void __init r8a7790_init_early(void)
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{
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#ifndef CONFIG_ARM_ARCH_TIMER
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shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
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#endif
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}
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#ifdef CONFIG_USE_OF
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static const char * const r8a7790_boards_compat_dt[] __initconst = {
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"renesas,r8a7790",
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NULL,
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};
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DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
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.smp = smp_ops(r8a7790_smp_ops),
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.init_early = r8a7790_init_early,
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.init_time = rcar_gen2_timer_init,
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.dt_compat = r8a7790_boards_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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