mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 02:34:01 +08:00
d59288b757
- remove __{,test_and_}{set,clear,change}_bit() and test_bit()
- remove ffz()
- remove __ffs()
- remove sched_find_first_bit()
- remove ffs()
- remove generic_fls()
- remove generic_fls64()
- remove generic_hweight{32,16,8}()
- remove find_{next,first}{,_zero}_bit()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove ext2_{set,clear}_bit_atomic()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: William Lee Irwin III <wli@holomorphy.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
175 lines
4.7 KiB
C
175 lines
4.7 KiB
C
/* $Id: bitops.h,v 1.67 2001/11/19 18:36:34 davem Exp $
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* bitops.h: Bit string operations on the Sparc.
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*
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* Copyright 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright 1996 Eddie C. Dost (ecd@skynet.be)
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* Copyright 2001 Anton Blanchard (anton@samba.org)
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*/
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#ifndef _SPARC_BITOPS_H
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#define _SPARC_BITOPS_H
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#include <linux/compiler.h>
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#include <asm/byteorder.h>
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#ifdef __KERNEL__
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/*
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* Set bit 'nr' in 32-bit quantity at address 'addr' where bit '0'
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* is in the highest of the four bytes and bit '31' is the high bit
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* within the first byte. Sparc is BIG-Endian. Unless noted otherwise
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* all bit-ops return 0 if bit was previously clear and != 0 otherwise.
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*/
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static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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register unsigned long mask asm("g2");
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register unsigned long *ADDR asm("g1");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g5");
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register int tmp4 asm("g7");
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ADDR = ((unsigned long *) addr) + (nr >> 5);
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mask = 1 << (nr & 31);
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___set_bit\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
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: "0" (mask), "r" (ADDR)
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: "memory", "cc");
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return mask != 0;
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}
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static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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register unsigned long mask asm("g2");
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register unsigned long *ADDR asm("g1");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g5");
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register int tmp4 asm("g7");
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ADDR = ((unsigned long *) addr) + (nr >> 5);
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mask = 1 << (nr & 31);
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___set_bit\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
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: "0" (mask), "r" (ADDR)
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: "memory", "cc");
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}
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static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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register unsigned long mask asm("g2");
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register unsigned long *ADDR asm("g1");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g5");
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register int tmp4 asm("g7");
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ADDR = ((unsigned long *) addr) + (nr >> 5);
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mask = 1 << (nr & 31);
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___clear_bit\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
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: "0" (mask), "r" (ADDR)
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: "memory", "cc");
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return mask != 0;
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}
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static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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register unsigned long mask asm("g2");
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register unsigned long *ADDR asm("g1");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g5");
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register int tmp4 asm("g7");
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ADDR = ((unsigned long *) addr) + (nr >> 5);
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mask = 1 << (nr & 31);
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___clear_bit\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
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: "0" (mask), "r" (ADDR)
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: "memory", "cc");
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}
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static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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register unsigned long mask asm("g2");
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register unsigned long *ADDR asm("g1");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g5");
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register int tmp4 asm("g7");
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ADDR = ((unsigned long *) addr) + (nr >> 5);
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mask = 1 << (nr & 31);
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___change_bit\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
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: "0" (mask), "r" (ADDR)
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: "memory", "cc");
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return mask != 0;
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}
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static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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register unsigned long mask asm("g2");
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register unsigned long *ADDR asm("g1");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g5");
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register int tmp4 asm("g7");
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ADDR = ((unsigned long *) addr) + (nr >> 5);
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mask = 1 << (nr & 31);
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___change_bit\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (mask), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4)
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: "0" (mask), "r" (ADDR)
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: "memory", "cc");
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}
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#include <asm-generic/bitops/non-atomic.h>
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#define smp_mb__before_clear_bit() do { } while(0)
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#define smp_mb__after_clear_bit() do { } while(0)
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#include <asm-generic/bitops/ffz.h>
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#include <asm-generic/bitops/__ffs.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/ffs.h>
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#include <asm-generic/bitops/fls.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/find.h>
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#include <asm-generic/bitops/ext2-non-atomic.h>
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#include <asm-generic/bitops/ext2-atomic.h>
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#include <asm-generic/bitops/minix.h>
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#endif /* __KERNEL__ */
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#endif /* defined(_SPARC_BITOPS_H) */
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