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b43ab901d6
Sodaville has GPIO controller behind the PCI bus. To my suprissed it is not the same as on PXA. The interrupt & gpio chip can be referenced from the device tree like from any other driver. Unfortunately the driver which uses the gpio interrupt has to use irq_of_parse_and_map() instead of platform_get_irq(). The problem is that the platform device (which is created from the device tree) is most likely created before the interrupt chip is registered and therefore irq_of_parse_and_map() fails. In theory the driver works as module. In reality most of the irq functions are not exported to modules and it is possible that _this_ module is unloaded while the provided irqs are still in use. Signed-off-by: Hans J. Koch <hjk@linutronix.de> [torbenh@linutronix.de: make it work after the irq namespace cleanup, add some device tree entries.] Signed-off-by: Torben Hohn <torbenh@linutronix.de> [bigeasy@linutronix.de: convert to generic irq & gpio chip] Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> [grant.likely@secretlab.ca: depend on x86 to avoid irq_domain breakage] Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
49 lines
1.5 KiB
Plaintext
49 lines
1.5 KiB
Plaintext
GPIO controller on CE4100 / Sodaville SoCs
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==========================================
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The bindings for CE4100's GPIO controller match the generic description
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which is covered by the gpio.txt file in this folder.
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The only additional property is the intel,muxctl property which holds the
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value which is written into the MUXCNTL register.
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There is no compatible property for now because the driver is probed via
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PCI id (vendor 0x8086 device 0x2e67).
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The interrupt specifier consists of two cells encoded as follows:
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- <1st cell>: The interrupt-number that identifies the interrupt source.
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- <2nd cell>: The level-sense information, encoded as follows:
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4 - active high level-sensitive
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8 - active low level-sensitive
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Example of the GPIO device and one user:
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pcigpio: gpio@b,1 {
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/* two cells for GPIO and interrupt */
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "pci8086,2e67.2",
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"pci8086,2e67",
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"pciclassff0000",
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"pciclassff00";
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reg = <0x15900 0x0 0x0 0x0 0x0>;
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/* Interrupt line of the gpio device */
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interrupts = <15 1>;
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/* It is an interrupt and GPIO controller itself */
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interrupt-controller;
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gpio-controller;
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intel,muxctl = <0>;
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};
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testuser@20 {
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compatible = "example,testuser";
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/* User the 11th GPIO line as an active high triggered
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* level interrupt
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*/
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interrupts = <11 8>;
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interrupt-parent = <&pcigpio>;
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/* Use this GPIO also with the gpio functions */
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gpios = <&pcigpio 11 0>;
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};
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