Chris Metcalf abe3265a6d tile: do less L1 I-cache eviction ... We had been doing an automatic full eviction of the L1 I$ everywhere whenever we did a kernel-space TLB flush. It turns out this isn't necessary, since all the callers already handle doing a flush if necessary. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>		2013-08-30 11:56:34 -04:00
..
configs	md: remove CONFIG_MULTICORE_RAID456 entirely	2013-03-20 13:21:14 +11:00
gxio	tile PCI RC: support more MSI-X interrupt vectors	2013-08-06 12:55:24 -04:00
include	tile: support ASLR fully	2013-08-30 11:56:25 -04:00
kernel	tile: do less L1 I-cache eviction	2013-08-30 11:56:34 -04:00
kvm	arch/tile/kvm: remove depends on CONFIG_EXPERIMENTAL	2013-01-17 12:11:26 -08:00
lib	tile: use proper .align directives on __ex_table sections	2013-08-30 11:56:11 -04:00
mm	tile: support ASLR fully	2013-08-30 11:56:25 -04:00
Kbuild	arch/tile: core support for Tilera 32-bit chips.	2010-06-04 17:11:18 -04:00
Kconfig	tile: support kprobes on tilegx	2013-08-30 11:55:53 -04:00
Kconfig.debug	tile: provide traceability for hypervisor calls	2013-08-13 16:26:31 -04:00
Makefile	arch/tile: avoid generating .eh_frame information in modules	2012-10-23 10:21:43 -04:00