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de0b632ba0
This changes the thresholds for the liquid cooled G5 thermal shutdown mechanism to prevent an errant shutdown with some models. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
327 lines
9.3 KiB
C
327 lines
9.3 KiB
C
#ifndef __THERM_PMAC_7_2_H__
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#define __THERM_PMAC_7_2_H__
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typedef unsigned short fu16;
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typedef int fs32;
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typedef short fs16;
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struct mpu_data
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{
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u8 signature; /* 0x00 - EEPROM sig. */
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u8 bytes_used; /* 0x01 - Bytes used in eeprom (160 ?) */
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u8 size; /* 0x02 - EEPROM size (256 ?) */
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u8 version; /* 0x03 - EEPROM version */
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u32 data_revision; /* 0x04 - Dataset revision */
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u8 processor_bin_code[3]; /* 0x08 - Processor BIN code */
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u8 bin_code_expansion; /* 0x0b - ??? (padding ?) */
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u8 processor_num; /* 0x0c - Number of CPUs on this MPU */
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u8 input_mul_bus_div; /* 0x0d - Clock input multiplier/bus divider */
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u8 reserved1[2]; /* 0x0e - */
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u32 input_clk_freq_high; /* 0x10 - Input clock frequency high */
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u8 cpu_nb_target_cycles; /* 0x14 - ??? */
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u8 cpu_statlat; /* 0x15 - ??? */
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u8 cpu_snooplat; /* 0x16 - ??? */
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u8 cpu_snoopacc; /* 0x17 - ??? */
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u8 nb_paamwin; /* 0x18 - ??? */
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u8 nb_statlat; /* 0x19 - ??? */
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u8 nb_snooplat; /* 0x1a - ??? */
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u8 nb_snoopwin; /* 0x1b - ??? */
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u8 api_bus_mode; /* 0x1c - ??? */
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u8 reserved2[3]; /* 0x1d - */
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u32 input_clk_freq_low; /* 0x20 - Input clock frequency low */
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u8 processor_card_slot; /* 0x24 - Processor card slot number */
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u8 reserved3[2]; /* 0x25 - */
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u8 padjmax; /* 0x27 - Max power adjustment (Not in OF!) */
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u8 ttarget; /* 0x28 - Target temperature */
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u8 tmax; /* 0x29 - Max temperature */
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u8 pmaxh; /* 0x2a - Max power */
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u8 tguardband; /* 0x2b - Guardband temp ??? Hist. len in OSX */
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fs32 pid_gp; /* 0x2c - PID proportional gain */
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fs32 pid_gr; /* 0x30 - PID reset gain */
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fs32 pid_gd; /* 0x34 - PID derivative gain */
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fu16 voph; /* 0x38 - Vop High */
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fu16 vopl; /* 0x3a - Vop Low */
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fs16 nactual_die; /* 0x3c - nActual Die */
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fs16 nactual_heatsink; /* 0x3e - nActual Heatsink */
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fs16 nactual_system; /* 0x40 - nActual System */
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u16 calibration_flags; /* 0x42 - Calibration flags */
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fu16 mdiode; /* 0x44 - Diode M value (scaling factor) */
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fs16 bdiode; /* 0x46 - Diode B value (offset) */
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fs32 theta_heat_sink; /* 0x48 - Theta heat sink */
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u16 rminn_intake_fan; /* 0x4c - Intake fan min RPM */
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u16 rmaxn_intake_fan; /* 0x4e - Intake fan max RPM */
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u16 rminn_exhaust_fan; /* 0x50 - Exhaust fan min RPM */
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u16 rmaxn_exhaust_fan; /* 0x52 - Exhaust fan max RPM */
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u8 processor_part_num[8]; /* 0x54 - Processor part number XX pumps min/max */
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u32 processor_lot_num; /* 0x5c - Processor lot number */
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u8 orig_card_sernum[0x10]; /* 0x60 - Card original serial number */
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u8 curr_card_sernum[0x10]; /* 0x70 - Card current serial number */
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u8 mlb_sernum[0x18]; /* 0x80 - MLB serial number */
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u32 checksum1; /* 0x98 - */
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u32 checksum2; /* 0x9c - */
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}; /* Total size = 0xa0 */
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/* Display a 16.16 fixed point value */
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#define FIX32TOPRINT(f) ((f) >> 16),((((f) & 0xffff) * 1000) >> 16)
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/*
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* Maximum number of seconds to be in critical state (after a
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* normal shutdown attempt). If the machine isn't down after
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* this counter elapses, we force an immediate machine power
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* off.
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*/
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#define MAX_CRITICAL_STATE 30
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static char * critical_overtemp_path = "/sbin/critical_overtemp";
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/*
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* This option is "weird" :) Basically, if you define this to 1
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* the control loop for the RPMs fans (not PWMs) will apply the
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* correction factor obtained from the PID to the _actual_ RPM
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* speed read from the FCU.
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* If you define the below constant to 0, then it will be
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* applied to the setpoint RPM speed, that is basically the
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* speed we proviously "asked" for.
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*
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* I'm not sure which of these Apple's algorithm is supposed
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* to use
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*/
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#define RPM_PID_USE_ACTUAL_SPEED 0
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/*
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* i2c IDs. Currently, we hard code those and assume that
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* the FCU is on U3 bus 1 while all sensors are on U3 bus
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* 0. This appear to be safe enough for this first version
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* of the driver, though I would accept any clean patch
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* doing a better use of the device-tree without turning the
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* while i2c registration mechanism into a racy mess
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*
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* Note: Xserve changed this. We have some bits on the K2 bus,
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* which I arbitrarily set to 0x200. Ultimately, we really want
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* too lookup these in the device-tree though
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*/
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#define FAN_CTRLER_ID 0x15e
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#define SUPPLY_MONITOR_ID 0x58
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#define SUPPLY_MONITORB_ID 0x5a
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#define DRIVES_DALLAS_ID 0x94
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#define BACKSIDE_MAX_ID 0x98
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#define XSERVE_DIMMS_LM87 0x25a
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#define XSERVE_SLOTS_LM75 0x290
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/*
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* Some MAX6690, DS1775, LM87 register definitions
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*/
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#define MAX6690_INT_TEMP 0
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#define MAX6690_EXT_TEMP 1
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#define DS1775_TEMP 0
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#define LM87_INT_TEMP 0x27
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/*
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* Scaling factors for the AD7417 ADC converters (except
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* for the CPU diode which is obtained from the EEPROM).
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* Those values are obtained from the property list of
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* the darwin driver
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*/
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#define ADC_12V_CURRENT_SCALE 0x0320 /* _AD2 */
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#define ADC_CPU_VOLTAGE_SCALE 0x00a0 /* _AD3 */
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#define ADC_CPU_CURRENT_SCALE 0x1f40 /* _AD4 */
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/*
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* PID factors for the U3/Backside fan control loop. We have 2 sets
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* of values here, one set for U3 and one set for U3H
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*/
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#define BACKSIDE_FAN_PWM_DEFAULT_ID 1
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#define BACKSIDE_FAN_PWM_INDEX 0
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#define BACKSIDE_PID_U3_G_d 0x02800000
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#define BACKSIDE_PID_U3H_G_d 0x01400000
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#define BACKSIDE_PID_RACK_G_d 0x00500000
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#define BACKSIDE_PID_G_p 0x00500000
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#define BACKSIDE_PID_RACK_G_p 0x0004cccc
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#define BACKSIDE_PID_G_r 0x00000000
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#define BACKSIDE_PID_U3_INPUT_TARGET 0x00410000
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#define BACKSIDE_PID_U3H_INPUT_TARGET 0x004b0000
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#define BACKSIDE_PID_RACK_INPUT_TARGET 0x00460000
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#define BACKSIDE_PID_INTERVAL 5
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#define BACKSIDE_PID_RACK_INTERVAL 1
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#define BACKSIDE_PID_OUTPUT_MAX 100
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#define BACKSIDE_PID_U3_OUTPUT_MIN 20
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#define BACKSIDE_PID_U3H_OUTPUT_MIN 20
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#define BACKSIDE_PID_HISTORY_SIZE 2
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struct basckside_pid_params
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{
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s32 G_d;
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s32 G_p;
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s32 G_r;
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s32 input_target;
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s32 output_min;
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s32 output_max;
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s32 interval;
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int additive;
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};
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struct backside_pid_state
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{
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int ticks;
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struct i2c_client * monitor;
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s32 sample_history[BACKSIDE_PID_HISTORY_SIZE];
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s32 error_history[BACKSIDE_PID_HISTORY_SIZE];
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int cur_sample;
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s32 last_temp;
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int pwm;
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int first;
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};
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/*
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* PID factors for the Drive Bay fan control loop
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*/
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#define DRIVES_FAN_RPM_DEFAULT_ID 2
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#define DRIVES_FAN_RPM_INDEX 1
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#define DRIVES_PID_G_d 0x01e00000
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#define DRIVES_PID_G_p 0x00500000
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#define DRIVES_PID_G_r 0x00000000
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#define DRIVES_PID_INPUT_TARGET 0x00280000
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#define DRIVES_PID_INTERVAL 5
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#define DRIVES_PID_OUTPUT_MAX 4000
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#define DRIVES_PID_OUTPUT_MIN 300
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#define DRIVES_PID_HISTORY_SIZE 2
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struct drives_pid_state
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{
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int ticks;
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struct i2c_client * monitor;
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s32 sample_history[BACKSIDE_PID_HISTORY_SIZE];
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s32 error_history[BACKSIDE_PID_HISTORY_SIZE];
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int cur_sample;
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s32 last_temp;
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int rpm;
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int first;
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};
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#define SLOTS_FAN_PWM_DEFAULT_ID 2
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#define SLOTS_FAN_PWM_INDEX 2
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#define SLOTS_FAN_DEFAULT_PWM 40 /* Do better here ! */
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/*
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* PID factors for the Xserve DIMM control loop
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*/
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#define DIMM_PID_G_d 0
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#define DIMM_PID_G_p 0
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#define DIMM_PID_G_r 0x06553600
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#define DIMM_PID_INPUT_TARGET 3276800
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#define DIMM_PID_INTERVAL 1
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#define DIMM_PID_OUTPUT_MAX 14000
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#define DIMM_PID_OUTPUT_MIN 4000
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#define DIMM_PID_HISTORY_SIZE 20
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struct dimm_pid_state
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{
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int ticks;
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struct i2c_client * monitor;
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s32 sample_history[DIMM_PID_HISTORY_SIZE];
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s32 error_history[DIMM_PID_HISTORY_SIZE];
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int cur_sample;
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s32 last_temp;
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int first;
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int output;
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};
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/*
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* PID factors for the Xserve Slots control loop
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*/
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#define SLOTS_PID_G_d 0
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#define SLOTS_PID_G_p 0
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#define SLOTS_PID_G_r 0x00100000
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#define SLOTS_PID_INPUT_TARGET 3200000
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#define SLOTS_PID_INTERVAL 1
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#define SLOTS_PID_OUTPUT_MAX 100
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#define SLOTS_PID_OUTPUT_MIN 20
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#define SLOTS_PID_HISTORY_SIZE 20
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struct slots_pid_state
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{
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int ticks;
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struct i2c_client * monitor;
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s32 sample_history[SLOTS_PID_HISTORY_SIZE];
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s32 error_history[SLOTS_PID_HISTORY_SIZE];
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int cur_sample;
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s32 last_temp;
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int first;
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int pwm;
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};
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/* Desktops */
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#define CPUA_INTAKE_FAN_RPM_DEFAULT_ID 3
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#define CPUA_EXHAUST_FAN_RPM_DEFAULT_ID 4
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#define CPUB_INTAKE_FAN_RPM_DEFAULT_ID 5
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#define CPUB_EXHAUST_FAN_RPM_DEFAULT_ID 6
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#define CPUA_INTAKE_FAN_RPM_INDEX 3
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#define CPUA_EXHAUST_FAN_RPM_INDEX 4
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#define CPUB_INTAKE_FAN_RPM_INDEX 5
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#define CPUB_EXHAUST_FAN_RPM_INDEX 6
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#define CPU_INTAKE_SCALE 0x0000f852
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#define CPU_TEMP_HISTORY_SIZE 2
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#define CPU_POWER_HISTORY_SIZE 10
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#define CPU_PID_INTERVAL 1
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#define CPU_MAX_OVERTEMP 90
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#define CPUA_PUMP_RPM_INDEX 7
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#define CPUB_PUMP_RPM_INDEX 8
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#define CPU_PUMP_OUTPUT_MAX 3200
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#define CPU_PUMP_OUTPUT_MIN 1250
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/* Xserve */
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#define CPU_A1_FAN_RPM_INDEX 9
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#define CPU_A2_FAN_RPM_INDEX 10
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#define CPU_A3_FAN_RPM_INDEX 11
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#define CPU_B1_FAN_RPM_INDEX 12
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#define CPU_B2_FAN_RPM_INDEX 13
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#define CPU_B3_FAN_RPM_INDEX 14
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struct cpu_pid_state
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{
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int index;
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struct i2c_client * monitor;
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struct mpu_data mpu;
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int overtemp;
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s32 temp_history[CPU_TEMP_HISTORY_SIZE];
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int cur_temp;
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s32 power_history[CPU_POWER_HISTORY_SIZE];
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s32 error_history[CPU_POWER_HISTORY_SIZE];
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int cur_power;
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int count_power;
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int rpm;
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int intake_rpm;
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s32 voltage;
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s32 current_a;
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s32 last_temp;
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s32 last_power;
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int first;
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u8 adc_config;
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s32 pump_min;
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s32 pump_max;
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};
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/* Tickle FCU every 10 seconds */
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#define FCU_TICKLE_TICKS 10
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/*
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* Driver state
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*/
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enum {
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state_detached,
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state_attaching,
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state_attached,
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state_detaching,
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};
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#endif /* __THERM_PMAC_7_2_H__ */
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