mirror of
https://github.com/edk2-porting/linux-next.git
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8186749621
core: - add user def flag to cmd line modes - dma_fence_wait added might_sleep - dma-fence lockdep annotations - indefinite fences are bad documentation - gem CMA functions used in more drivers - struct mutex removal - more drm_ debug macro usage - set/drop master api fixes - fix for drm/mm hole size comparison - drm/mm remove invalid entry optimization - optimise drm/mm hole handling - VRR debugfs added - uncompressed AFBC modifier support - multiple display id blocks in EDID - multiple driver sg handling fixes - __drm_atomic_helper_crtc_reset in all drivers - managed vram helpers ttm: - ttm_mem_reg handling cleanup - remove bo offset field - drop CMA memtype flag - drop mappable flag xilinx: - New Xilinx ZynqMP DisplayPort Subsystem driver nouveau: - add CRC support - start using NVIDIA published class header files - convert all push buffer emission to new macros - Proper push buffer space management for EVO/NVD channels. - firmware loading fixes - 2MiB system memory pages support on Pascal and newer vkms: - larget cursor support i915: - Rocketlake platform enablement - Early DG1 enablement - Numerous GEM refactorings - DP MST fixes - FBC, PSR, Cursor, Color, Gamma fixes - TGL, RKL, EHL workaround updates - TGL 8K display support fixes - SDVO/HDMI/DVI fixes amdgpu: - Initial support for Sienna Cichlid GPU - Initial support for Navy Flounder GPU - SI UVD/VCE support - expose rotation property - Add support for unique id on Arcturus - Enable runtime PM on vega10 boards that support BACO - Skip BAR resizing if the bios already did id - Major swSMU code cleanup - Fixes for DCN bandwidth calculations amdkfd: - Track SDMA usage per process - SMI events interface radeon: - Default to on chip GART for AGP boards on all arches - Runtime PM reference count fixes msm: - headers regenerated causing churn - a650/a640 display and GPU enablement - dpu dither support for 6bpc panels - dpu cursor fix - dsi/mdp5 enablement for sdm630/sdm636/sdm66 tegra: - video capture prep support - reflection support mediatek: - convert mtk_dsi to bridge API meson: - FBC support sun4i: - iommu support rockchip: - register locking fix - per-pixel alpha support PX30 VOP - mgag200: - ported to simple and shmem helpers - device init cleanups - use managed pci functions - dropped hw cursor support ast: - use managed pci functions - use managed VRAM helpers - rework cursor support malidp: - dev_groups support hibmc: - refactor hibmc_drv_vdac: vc4: - create TXP CRTC imx: - error path fixes and cleanups etnaviv: - clock handling and error handling cleanups - use pin_user_pages -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJfK1atAAoJEAx081l5xIa+vDkQAJvl/mjbEA7fDy8Ysa0cgPLI 8nI4Bo/MaxkyRfUcP8+f/n3QQrRME37C0xa/Mn6SG1oFAdlovPwDqmDr5kjhkrMI geo8oJb2Q+AsrJr+ejpuF+iq0FxWi64bLbwJFJ2nBet+lHTMzoPceWeq3gG1Vvfl h6PV4B/9TjrnbhcKLIQSEmJ0kZp9uMkDBF/iynVn4+AKAkG1rQNjigdTH48IFPoz 28KuqG0B4NWu648zYXhjsN0kD3Dxjv3YOH+FsoWQpQa9icCTySYbySsQ7l0/XvA3 4BPtP3rWMhU46FHTBkWF72WQR4F0B4wm5DJJKMeG4vb1mXakOqAKcAq7JAbka+wL PBIiU+AcAKRSiwHmYDuDWtDoSpvYncuo0p3IvNP5hhih+7hqCnLIULDWS+V8AUzW 39usS/DXsVKk/HGYIYC89cRwsqWYD4c7edzOBdPQxW4LNYCD2gXezLJ5TeeR2lih y9JIVnPiluWleOovs4W3BoZNRuLc1rHBO6COToXjlme/48Z+sRHBAoge6UZurqRN jr+e60cS7n/DOeJQuNf4UHZnK48Pc24+3kVfMHlX+OKn8VuKPGr+USkeHV/NYL/B USiKCAxkkZM0dxerSb1/Ra9kGnchf0QBpA6Fsem8kV61Z4GVc+K6xJWg7KXB6n/3 7ZyalUKLwlOCz9sYsCCe =Yvtd -----END PGP SIGNATURE----- Merge tag 'drm-next-2020-08-06' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "New xilinx displayport driver, AMD support for two new GPUs (more header files), i915 initial support for RocketLake and some work on their DG1 (discrete chip). The core also grew some lockdep annotations to try and constrain what drivers do with dma-fences, and added some documentation on why the idea of indefinite fences doesn't work. The long list is below. I do have some fixes trees outstanding, but I'll follow up with those later. core: - add user def flag to cmd line modes - dma_fence_wait added might_sleep - dma-fence lockdep annotations - indefinite fences are bad documentation - gem CMA functions used in more drivers - struct mutex removal - more drm_ debug macro usage - set/drop master api fixes - fix for drm/mm hole size comparison - drm/mm remove invalid entry optimization - optimise drm/mm hole handling - VRR debugfs added - uncompressed AFBC modifier support - multiple display id blocks in EDID - multiple driver sg handling fixes - __drm_atomic_helper_crtc_reset in all drivers - managed vram helpers ttm: - ttm_mem_reg handling cleanup - remove bo offset field - drop CMA memtype flag - drop mappable flag xilinx: - New Xilinx ZynqMP DisplayPort Subsystem driver nouveau: - add CRC support - start using NVIDIA published class header files - convert all push buffer emission to new macros - Proper push buffer space management for EVO/NVD channels. - firmware loading fixes - 2MiB system memory pages support on Pascal and newer vkms: - larger cursor support i915: - Rocketlake platform enablement - Early DG1 enablement - Numerous GEM refactorings - DP MST fixes - FBC, PSR, Cursor, Color, Gamma fixes - TGL, RKL, EHL workaround updates - TGL 8K display support fixes - SDVO/HDMI/DVI fixes amdgpu: - Initial support for Sienna Cichlid GPU - Initial support for Navy Flounder GPU - SI UVD/VCE support - expose rotation property - Add support for unique id on Arcturus - Enable runtime PM on vega10 boards that support BACO - Skip BAR resizing if the bios already did id - Major swSMU code cleanup - Fixes for DCN bandwidth calculations amdkfd: - Track SDMA usage per process - SMI events interface radeon: - Default to on chip GART for AGP boards on all arches - Runtime PM reference count fixes msm: - headers regenerated causing churn - a650/a640 display and GPU enablement - dpu dither support for 6bpc panels - dpu cursor fix - dsi/mdp5 enablement for sdm630/sdm636/sdm66 tegra: - video capture prep support - reflection support mediatek: - convert mtk_dsi to bridge API meson: - FBC support sun4i: - iommu support rockchip: - register locking fix - per-pixel alpha support PX30 VOP mgag200: - ported to simple and shmem helpers - device init cleanups - use managed pci functions - dropped hw cursor support ast: - use managed pci functions - use managed VRAM helpers - rework cursor support malidp: - dev_groups support hibmc: - refactor hibmc_drv_vdac: vc4: - create TXP CRTC imx: - error path fixes and cleanups etnaviv: - clock handling and error handling cleanups - use pin_user_pages" * tag 'drm-next-2020-08-06' of git://anongit.freedesktop.org/drm/drm: (1747 commits) drm/msm: use kthread_create_worker instead of kthread_run drm/msm/mdp5: Add MDP5 configuration for SDM636/660 drm/msm/dsi: Add DSI configuration for SDM660 drm/msm/mdp5: Add MDP5 configuration for SDM630 drm/msm/dsi: Add phy configuration for SDM630/636/660 drm/msm/a6xx: add A640/A650 hwcg drm/msm/a6xx: hwcg tables in gpulist drm/msm/dpu: add SM8250 to hw catalog drm/msm/dpu: add SM8150 to hw catalog drm/msm/dpu: intf timing path for displayport drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3 drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845 drm/msm/dpu: move some sspp caps to dpu_caps drm/msm/dpu: update UBWC config for sm8150 and sm8250 drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250 drm/msm/a6xx: set ubwc config for A640 and A650 drm/msm/adreno: un-open-code some packets drm/msm: sync generated headers drm/msm/a6xx: add build_bw_table for A640/A650 drm/msm/a6xx: fix crashstate capture for A650 ...
378 lines
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378 lines
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====================
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DMA Engine API Guide
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====================
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Vinod Koul <vinod dot koul at intel.com>
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.. note:: For DMA Engine usage in async_tx please see:
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``Documentation/crypto/async-tx-api.rst``
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Below is a guide to device driver writers on how to use the Slave-DMA API of the
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DMA Engine. This is applicable only for slave DMA usage only.
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DMA usage
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=========
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The slave DMA usage consists of following steps:
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- Allocate a DMA slave channel
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- Set slave and controller specific parameters
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- Get a descriptor for transaction
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- Submit the transaction
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- Issue pending requests and wait for callback notification
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The details of these operations are:
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1. Allocate a DMA slave channel
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Channel allocation is slightly different in the slave DMA context,
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client drivers typically need a channel from a particular DMA
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controller only and even in some cases a specific channel is desired.
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To request a channel dma_request_chan() API is used.
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Interface:
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.. code-block:: c
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struct dma_chan *dma_request_chan(struct device *dev, const char *name);
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Which will find and return the ``name`` DMA channel associated with the 'dev'
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device. The association is done via DT, ACPI or board file based
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dma_slave_map matching table.
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A channel allocated via this interface is exclusive to the caller,
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until dma_release_channel() is called.
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2. Set slave and controller specific parameters
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Next step is always to pass some specific information to the DMA
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driver. Most of the generic information which a slave DMA can use
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is in struct dma_slave_config. This allows the clients to specify
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DMA direction, DMA addresses, bus widths, DMA burst lengths etc
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for the peripheral.
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If some DMA controllers have more parameters to be sent then they
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should try to embed struct dma_slave_config in their controller
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specific structure. That gives flexibility to client to pass more
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parameters, if required.
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Interface:
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.. code-block:: c
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int dmaengine_slave_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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Please see the dma_slave_config structure definition in dmaengine.h
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for a detailed explanation of the struct members. Please note
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that the 'direction' member will be going away as it duplicates the
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direction given in the prepare call.
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3. Get a descriptor for transaction
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For slave usage the various modes of slave transfers supported by the
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DMA-engine are:
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- slave_sg: DMA a list of scatter gather buffers from/to a peripheral
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- dma_cyclic: Perform a cyclic DMA operation from/to a peripheral till the
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operation is explicitly stopped.
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- interleaved_dma: This is common to Slave as well as M2M clients. For slave
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address of devices' fifo could be already known to the driver.
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Various types of operations could be expressed by setting
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appropriate values to the 'dma_interleaved_template' members. Cyclic
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interleaved DMA transfers are also possible if supported by the channel by
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setting the DMA_PREP_REPEAT transfer flag.
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A non-NULL return of this transfer API represents a "descriptor" for
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the given transaction.
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Interface:
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.. code-block:: c
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struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_data_direction direction,
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unsigned long flags);
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struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
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struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
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size_t period_len, enum dma_data_direction direction);
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struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
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struct dma_chan *chan, struct dma_interleaved_template *xt,
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unsigned long flags);
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The peripheral driver is expected to have mapped the scatterlist for
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the DMA operation prior to calling dmaengine_prep_slave_sg(), and must
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keep the scatterlist mapped until the DMA operation has completed.
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The scatterlist must be mapped using the DMA struct device.
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If a mapping needs to be synchronized later, dma_sync_*_for_*() must be
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called using the DMA struct device, too.
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So, normal setup should look like this:
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.. code-block:: c
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nr_sg = dma_map_sg(chan->device->dev, sgl, sg_len);
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if (nr_sg == 0)
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/* error */
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desc = dmaengine_prep_slave_sg(chan, sgl, nr_sg, direction, flags);
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Once a descriptor has been obtained, the callback information can be
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added and the descriptor must then be submitted. Some DMA engine
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drivers may hold a spinlock between a successful preparation and
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submission so it is important that these two operations are closely
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paired.
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.. note::
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Although the async_tx API specifies that completion callback
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routines cannot submit any new operations, this is not the
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case for slave/cyclic DMA.
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For slave DMA, the subsequent transaction may not be available
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for submission prior to callback function being invoked, so
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slave DMA callbacks are permitted to prepare and submit a new
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transaction.
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For cyclic DMA, a callback function may wish to terminate the
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DMA via dmaengine_terminate_async().
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Therefore, it is important that DMA engine drivers drop any
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locks before calling the callback function which may cause a
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deadlock.
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Note that callbacks will always be invoked from the DMA
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engines tasklet, never from interrupt context.
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**Optional: per descriptor metadata**
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DMAengine provides two ways for metadata support.
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DESC_METADATA_CLIENT
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The metadata buffer is allocated/provided by the client driver and it is
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attached to the descriptor.
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.. code-block:: c
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int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
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void *data, size_t len);
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DESC_METADATA_ENGINE
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The metadata buffer is allocated/managed by the DMA driver. The client
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driver can ask for the pointer, maximum size and the currently used size of
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the metadata and can directly update or read it.
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Becasue the DMA driver manages the memory area containing the metadata,
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clients must make sure that they do not try to access or get the pointer
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after their transfer completion callback has run for the descriptor.
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If no completion callback has been defined for the transfer, then the
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metadata must not be accessed after issue_pending.
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In other words: if the aim is to read back metadata after the transfer is
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completed, then the client must use completion callback.
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.. code-block:: c
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void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
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size_t *payload_len, size_t *max_len);
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int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
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size_t payload_len);
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Client drivers can query if a given mode is supported with:
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.. code-block:: c
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bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan,
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enum dma_desc_metadata_mode mode);
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Depending on the used mode client drivers must follow different flow.
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DESC_METADATA_CLIENT
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- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
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1. prepare the descriptor (dmaengine_prep_*)
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construct the metadata in the client's buffer
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2. use dmaengine_desc_attach_metadata() to attach the buffer to the
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descriptor
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3. submit the transfer
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- DMA_DEV_TO_MEM:
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1. prepare the descriptor (dmaengine_prep_*)
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2. use dmaengine_desc_attach_metadata() to attach the buffer to the
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descriptor
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3. submit the transfer
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4. when the transfer is completed, the metadata should be available in the
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attached buffer
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DESC_METADATA_ENGINE
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- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
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1. prepare the descriptor (dmaengine_prep_*)
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2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the
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engine's metadata area
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3. update the metadata at the pointer
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4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the
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amount of data the client has placed into the metadata buffer
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5. submit the transfer
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- DMA_DEV_TO_MEM:
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1. prepare the descriptor (dmaengine_prep_*)
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2. submit the transfer
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3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get
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the pointer to the engine's metadata area
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4. read out the metadata from the pointer
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.. note::
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When DESC_METADATA_ENGINE mode is used the metadata area for the descriptor
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is no longer valid after the transfer has been completed (valid up to the
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point when the completion callback returns if used).
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Mixed use of DESC_METADATA_CLIENT / DESC_METADATA_ENGINE is not allowed,
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client drivers must use either of the modes per descriptor.
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4. Submit the transaction
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Once the descriptor has been prepared and the callback information
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added, it must be placed on the DMA engine drivers pending queue.
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Interface:
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.. code-block:: c
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dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
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This returns a cookie can be used to check the progress of DMA engine
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activity via other DMA engine calls not covered in this document.
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dmaengine_submit() will not start the DMA operation, it merely adds
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it to the pending queue. For this, see step 5, dma_async_issue_pending.
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.. note::
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After calling ``dmaengine_submit()`` the submitted transfer descriptor
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(``struct dma_async_tx_descriptor``) belongs to the DMA engine.
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Consequently, the client must consider invalid the pointer to that
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descriptor.
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5. Issue pending DMA requests and wait for callback notification
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The transactions in the pending queue can be activated by calling the
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issue_pending API. If channel is idle then the first transaction in
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queue is started and subsequent ones queued up.
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On completion of each DMA operation, the next in queue is started and
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a tasklet triggered. The tasklet will then call the client driver
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completion callback routine for notification, if set.
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Interface:
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.. code-block:: c
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void dma_async_issue_pending(struct dma_chan *chan);
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Further APIs
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------------
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1. Terminate APIs
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.. code-block:: c
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int dmaengine_terminate_sync(struct dma_chan *chan)
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int dmaengine_terminate_async(struct dma_chan *chan)
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int dmaengine_terminate_all(struct dma_chan *chan) /* DEPRECATED */
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This causes all activity for the DMA channel to be stopped, and may
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discard data in the DMA FIFO which hasn't been fully transferred.
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No callback functions will be called for any incomplete transfers.
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Two variants of this function are available.
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dmaengine_terminate_async() might not wait until the DMA has been fully
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stopped or until any running complete callbacks have finished. But it is
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possible to call dmaengine_terminate_async() from atomic context or from
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within a complete callback. dmaengine_synchronize() must be called before it
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is safe to free the memory accessed by the DMA transfer or free resources
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accessed from within the complete callback.
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dmaengine_terminate_sync() will wait for the transfer and any running
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complete callbacks to finish before it returns. But the function must not be
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called from atomic context or from within a complete callback.
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dmaengine_terminate_all() is deprecated and should not be used in new code.
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2. Pause API
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.. code-block:: c
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int dmaengine_pause(struct dma_chan *chan)
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This pauses activity on the DMA channel without data loss.
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3. Resume API
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.. code-block:: c
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int dmaengine_resume(struct dma_chan *chan)
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Resume a previously paused DMA channel. It is invalid to resume a
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channel which is not currently paused.
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4. Check Txn complete
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.. code-block:: c
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enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
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dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
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This can be used to check the status of the channel. Please see
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the documentation in include/linux/dmaengine.h for a more complete
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description of this API.
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This can be used in conjunction with dma_async_is_complete() and
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the cookie returned from dmaengine_submit() to check for
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completion of a specific DMA transaction.
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.. note::
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Not all DMA engine drivers can return reliable information for
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a running DMA channel. It is recommended that DMA engine users
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pause or stop (via dmaengine_terminate_all()) the channel before
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using this API.
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5. Synchronize termination API
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.. code-block:: c
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void dmaengine_synchronize(struct dma_chan *chan)
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Synchronize the termination of the DMA channel to the current context.
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This function should be used after dmaengine_terminate_async() to synchronize
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the termination of the DMA channel to the current context. The function will
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wait for the transfer and any running complete callbacks to finish before it
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returns.
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If dmaengine_terminate_async() is used to stop the DMA channel this function
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must be called before it is safe to free memory accessed by previously
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submitted descriptors or to free any resources accessed within the complete
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callback of previously submitted descriptors.
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The behavior of this function is undefined if dma_async_issue_pending() has
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been called between dmaengine_terminate_async() and this function.
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