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255 lines
6.5 KiB
C
255 lines
6.5 KiB
C
/*
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* @file op_model_ppro.h
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* Family 6 perfmon and architectural perfmon MSR operations
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*
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* @remark Copyright 2002 OProfile authors
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* @remark Copyright 2008 Intel Corporation
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* @remark Read the file COPYING
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*
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* @author John Levon
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* @author Philippe Elie
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* @author Graydon Hoare
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* @author Andi Kleen
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*/
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#include <linux/oprofile.h>
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#include <linux/slab.h>
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#include <asm/ptrace.h>
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#include <asm/msr.h>
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#include <asm/apic.h>
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#include <asm/nmi.h>
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#include <asm/intel_arch_perfmon.h>
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#include "op_x86_model.h"
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#include "op_counter.h"
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static int num_counters = 2;
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static int counter_width = 32;
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#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
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#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
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#define CTR_OVERFLOWED(n) (!((n) & (1U<<(counter_width-1))))
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#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
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#define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
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#define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
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#define CTRL_SET_ACTIVE(n) (n |= (1<<22))
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#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
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#define CTRL_CLEAR(x) (x &= (1<<21))
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#define CTRL_SET_ENABLE(val) (val |= 1<<20)
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#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
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#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
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#define CTRL_SET_UM(val, m) (val |= (m << 8))
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#define CTRL_SET_EVENT(val, e) (val |= e)
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static u64 *reset_value;
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static void ppro_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < num_counters; i++) {
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if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
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msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
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else
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msrs->counters[i].addr = 0;
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}
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for (i = 0; i < num_counters; i++) {
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if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
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msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
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else
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msrs->controls[i].addr = 0;
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}
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}
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static void ppro_setup_ctrs(struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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int i;
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if (!reset_value) {
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reset_value = kmalloc(sizeof(unsigned) * num_counters,
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GFP_ATOMIC);
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if (!reset_value)
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return;
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}
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if (cpu_has_arch_perfmon) {
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union cpuid10_eax eax;
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eax.full = cpuid_eax(0xa);
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if (counter_width < eax.split.bit_width)
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counter_width = eax.split.bit_width;
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}
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/* clear all counters */
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for (i = 0 ; i < num_counters; ++i) {
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if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
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continue;
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CTRL_READ(low, high, msrs, i);
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CTRL_CLEAR(low);
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CTRL_WRITE(low, high, msrs, i);
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}
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/* avoid a false detection of ctr overflows in NMI handler */
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for (i = 0; i < num_counters; ++i) {
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if (unlikely(!CTR_IS_RESERVED(msrs, i)))
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continue;
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wrmsrl(msrs->counters[i].addr, -1LL);
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}
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/* enable active counters */
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for (i = 0; i < num_counters; ++i) {
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if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
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reset_value[i] = counter_config[i].count;
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wrmsrl(msrs->counters[i].addr, -reset_value[i]);
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CTRL_READ(low, high, msrs, i);
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CTRL_CLEAR(low);
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CTRL_SET_ENABLE(low);
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CTRL_SET_USR(low, counter_config[i].user);
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CTRL_SET_KERN(low, counter_config[i].kernel);
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CTRL_SET_UM(low, counter_config[i].unit_mask);
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CTRL_SET_EVENT(low, counter_config[i].event);
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CTRL_WRITE(low, high, msrs, i);
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} else {
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reset_value[i] = 0;
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}
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}
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}
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static int ppro_check_ctrs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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int i;
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for (i = 0 ; i < num_counters; ++i) {
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if (!reset_value[i])
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continue;
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CTR_READ(low, high, msrs, i);
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if (CTR_OVERFLOWED(low)) {
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oprofile_add_sample(regs, i);
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wrmsrl(msrs->counters[i].addr, -reset_value[i]);
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}
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}
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/* Only P6 based Pentium M need to re-unmask the apic vector but it
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* doesn't hurt other P6 variant */
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apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
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/* We can't work out if we really handled an interrupt. We
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* might have caught a *second* counter just after overflowing
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* the interrupt for this counter then arrives
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* and we don't find a counter that's overflowed, so we
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* would return 0 and get dazed + confused. Instead we always
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* assume we found an overflow. This sucks.
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*/
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return 1;
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}
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static void ppro_start(struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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int i;
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for (i = 0; i < num_counters; ++i) {
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if (reset_value[i]) {
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CTRL_READ(low, high, msrs, i);
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CTRL_SET_ACTIVE(low);
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CTRL_WRITE(low, high, msrs, i);
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}
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}
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}
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static void ppro_stop(struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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int i;
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for (i = 0; i < num_counters; ++i) {
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if (!reset_value[i])
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continue;
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CTRL_READ(low, high, msrs, i);
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CTRL_SET_INACTIVE(low);
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CTRL_WRITE(low, high, msrs, i);
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}
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}
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static void ppro_shutdown(struct op_msrs const * const msrs)
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{
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int i;
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for (i = 0 ; i < num_counters ; ++i) {
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if (CTR_IS_RESERVED(msrs, i))
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release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
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}
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for (i = 0 ; i < num_counters ; ++i) {
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if (CTRL_IS_RESERVED(msrs, i))
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release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
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}
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if (reset_value) {
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kfree(reset_value);
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reset_value = NULL;
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}
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}
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struct op_x86_model_spec op_ppro_spec = {
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.num_counters = 2, /* can be overriden */
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.num_controls = 2, /* dito */
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.fill_in_addresses = &ppro_fill_in_addresses,
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.setup_ctrs = &ppro_setup_ctrs,
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.check_ctrs = &ppro_check_ctrs,
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.start = &ppro_start,
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.stop = &ppro_stop,
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.shutdown = &ppro_shutdown
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};
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/*
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* Architectural performance monitoring.
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*
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* Newer Intel CPUs (Core1+) have support for architectural
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* events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
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* The advantage of this is that it can be done without knowing about
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* the specific CPU.
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*/
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void arch_perfmon_setup_counters(void)
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{
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union cpuid10_eax eax;
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eax.full = cpuid_eax(0xa);
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/* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
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if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
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current_cpu_data.x86_model == 15) {
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eax.split.version_id = 2;
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eax.split.num_counters = 2;
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eax.split.bit_width = 40;
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}
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num_counters = eax.split.num_counters;
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op_arch_perfmon_spec.num_counters = num_counters;
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op_arch_perfmon_spec.num_controls = num_counters;
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op_ppro_spec.num_counters = num_counters;
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op_ppro_spec.num_controls = num_counters;
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}
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struct op_x86_model_spec op_arch_perfmon_spec = {
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/* num_counters/num_controls filled in at runtime */
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.fill_in_addresses = &ppro_fill_in_addresses,
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/* user space does the cpuid check for available events */
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.setup_ctrs = &ppro_setup_ctrs,
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.check_ctrs = &ppro_check_ctrs,
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.start = &ppro_start,
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.stop = &ppro_stop,
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.shutdown = &ppro_shutdown
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};
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