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126ae9adc1
The default cache operations for ARM64 were changed during 3.15. To use coherent operations a "dma-coherent" device tree property is required. If that property is not present in the device tree node then the non-coherent operations are assigned for the device. Add support to the ccp driver to assign the AXI DMA cache settings based on whether the "dma-coherent" property is present in the device node. If present, use settings that work with the caches. If not present, use settings that do not look at the caches. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
20 lines
567 B
Plaintext
20 lines
567 B
Plaintext
* AMD Cryptographic Coprocessor driver (ccp)
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Required properties:
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- compatible: Should be "amd,ccp-seattle-v1a"
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- reg: Address and length of the register set for the device
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device
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- interrupts: Should contain the CCP interrupt
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Optional properties:
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- dma-coherent: Present if dma operations are coherent
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Example:
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ccp@e0100000 {
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compatible = "amd,ccp-seattle-v1a";
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reg = <0 0xe0100000 0 0x10000>;
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interrupt-parent = <&gic>;
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interrupts = <0 3 4>;
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};
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