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https://github.com/edk2-porting/linux-next.git
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a9e6141092
This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
289 lines
9.5 KiB
C
289 lines
9.5 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __RV770_DPM_H__
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#define __RV770_DPM_H__
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#include "rv770_smc.h"
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struct rv770_clock_registers {
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u32 cg_spll_func_cntl;
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u32 cg_spll_func_cntl_2;
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u32 cg_spll_func_cntl_3;
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u32 cg_spll_spread_spectrum;
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u32 cg_spll_spread_spectrum_2;
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u32 mpll_ad_func_cntl;
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u32 mpll_ad_func_cntl_2;
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u32 mpll_dq_func_cntl;
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u32 mpll_dq_func_cntl_2;
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u32 mclk_pwrmgt_cntl;
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u32 dll_cntl;
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u32 mpll_ss1;
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u32 mpll_ss2;
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};
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struct rv730_clock_registers {
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u32 cg_spll_func_cntl;
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u32 cg_spll_func_cntl_2;
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u32 cg_spll_func_cntl_3;
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u32 cg_spll_spread_spectrum;
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u32 cg_spll_spread_spectrum_2;
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u32 mclk_pwrmgt_cntl;
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u32 dll_cntl;
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u32 mpll_func_cntl;
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u32 mpll_func_cntl2;
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u32 mpll_func_cntl3;
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u32 mpll_ss;
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u32 mpll_ss2;
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};
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union r7xx_clock_registers {
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struct rv770_clock_registers rv770;
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struct rv730_clock_registers rv730;
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};
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struct vddc_table_entry {
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u16 vddc;
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u8 vddc_index;
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u8 high_smio;
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u32 low_smio;
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};
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#define MAX_NO_OF_MVDD_VALUES 2
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#define MAX_NO_VREG_STEPS 32
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struct rv7xx_power_info {
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/* flags */
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bool mem_gddr5;
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bool pcie_gen2;
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bool dynamic_pcie_gen2;
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bool acpi_pcie_gen2;
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bool boot_in_gen2;
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bool voltage_control; /* vddc */
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bool mvdd_control;
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bool sclk_ss;
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bool mclk_ss;
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bool dynamic_ss;
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bool gfx_clock_gating;
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bool mg_clock_gating;
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bool mgcgtssm;
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bool power_gating;
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bool thermal_protection;
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bool display_gap;
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bool dcodt;
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bool ulps;
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/* registers */
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union r7xx_clock_registers clk_regs;
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u32 s0_vid_lower_smio_cntl;
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/* voltage */
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u32 vddc_mask_low;
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u32 mvdd_mask_low;
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u32 mvdd_split_frequency;
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u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
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u16 max_vddc;
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u16 max_vddc_in_table;
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u16 min_vddc_in_table;
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struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
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u8 valid_vddc_entries;
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/* dc odt */
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u32 mclk_odt_threshold;
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u8 odt_value_0[2];
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u8 odt_value_1[2];
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/* stored values */
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u32 boot_sclk;
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u16 acpi_vddc;
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u32 ref_div;
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u32 active_auto_throttle_sources;
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u32 mclk_stutter_mode_threshold;
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u32 mclk_strobe_mode_threshold;
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u32 mclk_edc_enable_threshold;
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u32 bsp;
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u32 bsu;
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u32 pbsp;
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u32 pbsu;
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u32 dsp;
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u32 psp;
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u32 asi;
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u32 pasi;
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u32 vrc;
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u32 restricted_levels;
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u32 rlp;
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u32 rmp;
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u32 lhp;
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u32 lmp;
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/* smc offsets */
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u16 state_table_start;
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u16 soft_regs_start;
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u16 sram_end;
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/* scratch structs */
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RV770_SMC_STATETABLE smc_statetable;
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};
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struct rv7xx_pl {
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u32 sclk;
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u32 mclk;
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u16 vddc;
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u16 vddci; /* eg+ only */
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u32 flags;
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enum radeon_pcie_gen pcie_gen; /* si+ only */
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};
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struct rv7xx_ps {
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struct rv7xx_pl high;
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struct rv7xx_pl medium;
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struct rv7xx_pl low;
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bool dc_compatible;
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};
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#define RV770_RLP_DFLT 10
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#define RV770_RMP_DFLT 25
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#define RV770_LHP_DFLT 25
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#define RV770_LMP_DFLT 10
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#define RV770_VRC_DFLT 0x003f
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#define RV770_ASI_DFLT 1000
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#define RV770_HASI_DFLT 200000
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#define RV770_MGCGTTLOCAL0_DFLT 0x00100000
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#define RV7XX_MGCGTTLOCAL0_DFLT 0
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#define RV770_MGCGTTLOCAL1_DFLT 0xFFFF0000
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#define RV770_MGCGCGTSSMCTRL_DFLT 0x55940000
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#define MVDD_LOW_INDEX 0
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#define MVDD_HIGH_INDEX 1
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#define MVDD_LOW_VALUE 0
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#define MVDD_HIGH_VALUE 0xffff
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#define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */
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#define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */
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/* rv730/rv710 */
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int rv730_populate_sclk_value(struct radeon_device *rdev,
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u32 engine_clock,
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RV770_SMC_SCLK_VALUE *sclk);
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int rv730_populate_mclk_value(struct radeon_device *rdev,
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u32 engine_clock, u32 memory_clock,
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LPRV7XX_SMC_MCLK_VALUE mclk);
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void rv730_read_clock_registers(struct radeon_device *rdev);
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int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
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RV770_SMC_STATETABLE *table);
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int rv730_populate_smc_initial_state(struct radeon_device *rdev,
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struct radeon_ps *radeon_initial_state,
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RV770_SMC_STATETABLE *table);
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void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
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struct radeon_ps *radeon_state);
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void rv730_power_gating_enable(struct radeon_device *rdev,
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bool enable);
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void rv730_start_dpm(struct radeon_device *rdev);
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void rv730_stop_dpm(struct radeon_device *rdev);
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void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt);
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void rv730_get_odt_values(struct radeon_device *rdev);
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/* rv740 */
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int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
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RV770_SMC_SCLK_VALUE *sclk);
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int rv740_populate_mclk_value(struct radeon_device *rdev,
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u32 engine_clock, u32 memory_clock,
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RV7XX_SMC_MCLK_VALUE *mclk);
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void rv740_read_clock_registers(struct radeon_device *rdev);
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int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
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RV770_SMC_STATETABLE *table);
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void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
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bool enable);
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u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
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u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
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u32 rv740_get_decoded_reference_divider(u32 encoded_ref);
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/* rv770 */
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u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
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int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
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RV770_SMC_VOLTAGE_VALUE *voltage);
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int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
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RV770_SMC_VOLTAGE_VALUE *voltage);
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u8 rv770_get_seq_value(struct radeon_device *rdev,
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struct rv7xx_pl *pl);
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int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
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RV770_SMC_VOLTAGE_VALUE *voltage);
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u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
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u32 engine_clock);
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void rv770_program_response_times(struct radeon_device *rdev);
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int rv770_populate_smc_sp(struct radeon_device *rdev,
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struct radeon_ps *radeon_state,
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RV770_SMC_SWSTATE *smc_state);
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int rv770_populate_smc_t(struct radeon_device *rdev,
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struct radeon_ps *radeon_state,
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RV770_SMC_SWSTATE *smc_state);
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void rv770_read_voltage_smio_registers(struct radeon_device *rdev);
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void rv770_get_memory_type(struct radeon_device *rdev);
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void r7xx_start_smc(struct radeon_device *rdev);
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u8 rv770_get_memory_module_index(struct radeon_device *rdev);
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void rv770_get_max_vddc(struct radeon_device *rdev);
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void rv770_get_pcie_gen2_status(struct radeon_device *rdev);
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void rv770_enable_acpi_pm(struct radeon_device *rdev);
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void rv770_restore_cgcg(struct radeon_device *rdev);
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bool rv770_dpm_enabled(struct radeon_device *rdev);
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void rv770_enable_voltage_control(struct radeon_device *rdev,
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bool enable);
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void rv770_enable_backbias(struct radeon_device *rdev,
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bool enable);
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void rv770_enable_thermal_protection(struct radeon_device *rdev,
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bool enable);
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void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
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enum radeon_dpm_auto_throttle_src source,
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bool enable);
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void rv770_setup_bsp(struct radeon_device *rdev);
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void rv770_program_git(struct radeon_device *rdev);
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void rv770_program_tp(struct radeon_device *rdev);
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void rv770_program_tpp(struct radeon_device *rdev);
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void rv770_program_sstp(struct radeon_device *rdev);
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void rv770_program_engine_speed_parameters(struct radeon_device *rdev);
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void rv770_program_vc(struct radeon_device *rdev);
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void rv770_clear_vc(struct radeon_device *rdev);
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int rv770_upload_firmware(struct radeon_device *rdev);
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void rv770_stop_dpm(struct radeon_device *rdev);
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void r7xx_stop_smc(struct radeon_device *rdev);
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void rv770_reset_smio_status(struct radeon_device *rdev);
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int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
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int rv770_unrestrict_performance_levels_after_switch(struct radeon_device *rdev);
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int rv770_halt_smc(struct radeon_device *rdev);
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int rv770_resume_smc(struct radeon_device *rdev);
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int rv770_set_sw_state(struct radeon_device *rdev);
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int rv770_set_boot_state(struct radeon_device *rdev);
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int rv7xx_parse_power_table(struct radeon_device *rdev);
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void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
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struct radeon_ps *new_ps,
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struct radeon_ps *old_ps);
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void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
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struct radeon_ps *new_ps,
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struct radeon_ps *old_ps);
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/* smc */
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int rv770_read_smc_soft_register(struct radeon_device *rdev,
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u16 reg_offset, u32 *value);
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int rv770_write_smc_soft_register(struct radeon_device *rdev,
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u16 reg_offset, u32 value);
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/* thermal */
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int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
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int min_temp, int max_temp);
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#endif
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