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df71dfd4ca
Errata 411920 indicates that any "invalidate entire instruction cache" operation can fail if the right conditions are present. This is not limited just to those operations in flush.c, but elsewhere. Place the workaround in the already existing __flush_icache_all() function instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
/*
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* linux/arch/arm/mm/context.c
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*
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* Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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static DEFINE_SPINLOCK(cpu_asid_lock);
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unsigned int cpu_last_asid = ASID_FIRST_VERSION;
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/*
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* We fork()ed a process, and we need a new context for the child
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* to run in. We reserve version 0 for initial tasks so we will
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* always allocate an ASID. The ASID 0 is reserved for the TTBR
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* register changing sequence.
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*/
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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mm->context.id = 0;
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}
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void __new_context(struct mm_struct *mm)
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{
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unsigned int asid;
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spin_lock(&cpu_asid_lock);
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asid = ++cpu_last_asid;
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if (asid == 0)
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asid = cpu_last_asid = ASID_FIRST_VERSION;
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/*
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* If we've used up all our ASIDs, we need
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* to start a new version and flush the TLB.
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*/
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if (unlikely((asid & ~ASID_MASK) == 0)) {
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asid = ++cpu_last_asid;
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/* set the reserved ASID before flushing the TLB */
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asm("mcr p15, 0, %0, c13, c0, 1 @ set reserved context ID\n"
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:
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: "r" (0));
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isb();
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flush_tlb_all();
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if (icache_is_vivt_asid_tagged()) {
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__flush_icache_all();
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dsb();
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}
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}
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spin_unlock(&cpu_asid_lock);
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cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
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mm->context.id = asid;
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}
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