mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 14:43:58 +08:00
dfd871442e
All the clocks controlled by the register 'CCM Serial Clock Multiplexer Register 1' should be fixup clocks. This patch changes those clocks from basic multiplexer or divider clocks to fixup clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
113 lines
3.4 KiB
C
113 lines
3.4 KiB
C
#ifndef __MACH_IMX_CLK_H
|
|
#define __MACH_IMX_CLK_H
|
|
|
|
#include <linux/spinlock.h>
|
|
#include <linux/clk-provider.h>
|
|
|
|
extern spinlock_t imx_ccm_lock;
|
|
|
|
extern void imx_cscmr1_fixup(u32 *val);
|
|
|
|
struct clk *imx_clk_pllv1(const char *name, const char *parent,
|
|
void __iomem *base);
|
|
|
|
struct clk *imx_clk_pllv2(const char *name, const char *parent,
|
|
void __iomem *base);
|
|
|
|
enum imx_pllv3_type {
|
|
IMX_PLLV3_GENERIC,
|
|
IMX_PLLV3_SYS,
|
|
IMX_PLLV3_USB,
|
|
IMX_PLLV3_AV,
|
|
IMX_PLLV3_ENET,
|
|
};
|
|
|
|
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
|
|
const char *parent_name, void __iomem *base, u32 div_mask);
|
|
|
|
struct clk *clk_register_gate2(struct device *dev, const char *name,
|
|
const char *parent_name, unsigned long flags,
|
|
void __iomem *reg, u8 bit_idx,
|
|
u8 clk_gate_flags, spinlock_t *lock);
|
|
|
|
struct clk * imx_obtain_fixed_clock(
|
|
const char *name, unsigned long rate);
|
|
|
|
static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
|
|
void __iomem *reg, u8 shift)
|
|
{
|
|
return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
|
|
shift, 0, &imx_ccm_lock);
|
|
}
|
|
|
|
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
|
|
void __iomem *reg, u8 idx);
|
|
|
|
struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
void __iomem *busy_reg, u8 busy_shift);
|
|
|
|
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
|
|
u8 width, void __iomem *busy_reg, u8 busy_shift,
|
|
const char **parent_names, int num_parents);
|
|
|
|
struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
void (*fixup)(u32 *val));
|
|
|
|
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
|
|
u8 shift, u8 width, const char **parents,
|
|
int num_parents, void (*fixup)(u32 *val));
|
|
|
|
static inline struct clk *imx_clk_fixed(const char *name, int rate)
|
|
{
|
|
return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_divider(const char *name, const char *parent,
|
|
void __iomem *reg, u8 shift, u8 width)
|
|
{
|
|
return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
|
|
reg, shift, width, 0, &imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_divider_flags(const char *name,
|
|
const char *parent, void __iomem *reg, u8 shift, u8 width,
|
|
unsigned long flags)
|
|
{
|
|
return clk_register_divider(NULL, name, parent, flags,
|
|
reg, shift, width, 0, &imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_gate(const char *name, const char *parent,
|
|
void __iomem *reg, u8 shift)
|
|
{
|
|
return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
|
|
shift, 0, &imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
|
|
u8 shift, u8 width, const char **parents, int num_parents)
|
|
{
|
|
return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
|
|
width, 0, &imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_mux_flags(const char *name,
|
|
void __iomem *reg, u8 shift, u8 width, const char **parents,
|
|
int num_parents, unsigned long flags)
|
|
{
|
|
return clk_register_mux(NULL, name, parents, num_parents,
|
|
flags, reg, shift, width, 0,
|
|
&imx_ccm_lock);
|
|
}
|
|
|
|
static inline struct clk *imx_clk_fixed_factor(const char *name,
|
|
const char *parent, unsigned int mult, unsigned int div)
|
|
{
|
|
return clk_register_fixed_factor(NULL, name, parent,
|
|
CLK_SET_RATE_PARENT, mult, div);
|
|
}
|
|
|
|
#endif
|