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https://github.com/edk2-porting/linux-next.git
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9741b1a680
This patch adds common clock support for Mediatek SoCs, including plls, muxes and clock gates. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [sboyd@codeaurora.org: Squelch checkpatch warning in clk-mtk.h] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
138 lines
2.7 KiB
C
138 lines
2.7 KiB
C
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/clkdev.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_clk_gate(hw);
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u32 val;
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regmap_read(cg->regmap, cg->sta_ofs, &val);
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val &= BIT(cg->bit);
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return val == 0;
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}
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static int mtk_cg_bit_is_set(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_clk_gate(hw);
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u32 val;
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regmap_read(cg->regmap, cg->sta_ofs, &val);
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val &= BIT(cg->bit);
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return val != 0;
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}
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static void mtk_cg_set_bit(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_clk_gate(hw);
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regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
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}
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static void mtk_cg_clr_bit(struct clk_hw *hw)
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{
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struct mtk_clk_gate *cg = to_clk_gate(hw);
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regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
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}
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static int mtk_cg_enable(struct clk_hw *hw)
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{
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mtk_cg_clr_bit(hw);
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return 0;
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}
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static void mtk_cg_disable(struct clk_hw *hw)
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{
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mtk_cg_set_bit(hw);
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}
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static int mtk_cg_enable_inv(struct clk_hw *hw)
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{
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mtk_cg_set_bit(hw);
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return 0;
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}
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static void mtk_cg_disable_inv(struct clk_hw *hw)
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{
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mtk_cg_clr_bit(hw);
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}
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const struct clk_ops mtk_clk_gate_ops_setclr = {
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.is_enabled = mtk_cg_bit_is_cleared,
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.enable = mtk_cg_enable,
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.disable = mtk_cg_disable,
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};
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const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
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.is_enabled = mtk_cg_bit_is_set,
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.enable = mtk_cg_enable_inv,
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.disable = mtk_cg_disable_inv,
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};
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struct clk *mtk_clk_register_gate(
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const char *name,
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const char *parent_name,
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struct regmap *regmap,
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int set_ofs,
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int clr_ofs,
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int sta_ofs,
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u8 bit,
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const struct clk_ops *ops)
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{
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struct mtk_clk_gate *cg;
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struct clk *clk;
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struct clk_init_data init;
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cg = kzalloc(sizeof(*cg), GFP_KERNEL);
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if (!cg)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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init.ops = ops;
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cg->regmap = regmap;
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cg->set_ofs = set_ofs;
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cg->clr_ofs = clr_ofs;
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cg->sta_ofs = sta_ofs;
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cg->bit = bit;
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cg->hw.init = &init;
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clk = clk_register(NULL, &cg->hw);
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if (IS_ERR(clk))
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kfree(cg);
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return clk;
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}
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