mirror of
https://github.com/edk2-porting/linux-next.git
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baf4974e49
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input: Input: i8042 - print debug data when testing AUX IRQ delivery Input: libps2 - fix dependancy on i8042 Input: fix rx51 board keymap Input: ad7879 - pass up error codes from probe functions Input: xpad - add BigBen Interactive XBOX 360 Controller Input: rotary_encoder - fix relative axis support Input: sparkspkr - move remove() functions to .devexit.text Input: wistron_btns - add DMI entry for Medion WIM2030 laptop
484 lines
14 KiB
C
484 lines
14 KiB
C
/*
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* twl4030.h - header for TWL4030 PM and audio CODEC device
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*
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* Copyright (C) 2005-2006 Texas Instruments, Inc.
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*
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* Based on tlv320aic23.c:
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* Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __TWL4030_H_
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#define __TWL4030_H_
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#include <linux/types.h>
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#include <linux/input/matrix_keypad.h>
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/*
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* Using the twl4030 core we address registers using a pair
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* { module id, relative register offset }
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* which that core then maps to the relevant
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* { i2c slave, absolute register address }
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*
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* The module IDs are meaningful only to the twl4030 core code,
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* which uses them as array indices to look up the first register
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* address each module uses within a given i2c slave.
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*/
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/* Slave 0 (i2c address 0x48) */
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#define TWL4030_MODULE_USB 0x00
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/* Slave 1 (i2c address 0x49) */
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#define TWL4030_MODULE_AUDIO_VOICE 0x01
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#define TWL4030_MODULE_GPIO 0x02
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#define TWL4030_MODULE_INTBR 0x03
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#define TWL4030_MODULE_PIH 0x04
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#define TWL4030_MODULE_TEST 0x05
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/* Slave 2 (i2c address 0x4a) */
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#define TWL4030_MODULE_KEYPAD 0x06
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#define TWL4030_MODULE_MADC 0x07
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#define TWL4030_MODULE_INTERRUPTS 0x08
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#define TWL4030_MODULE_LED 0x09
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#define TWL4030_MODULE_MAIN_CHARGE 0x0A
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#define TWL4030_MODULE_PRECHARGE 0x0B
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#define TWL4030_MODULE_PWM0 0x0C
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#define TWL4030_MODULE_PWM1 0x0D
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#define TWL4030_MODULE_PWMA 0x0E
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#define TWL4030_MODULE_PWMB 0x0F
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/* Slave 3 (i2c address 0x4b) */
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#define TWL4030_MODULE_BACKUP 0x10
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#define TWL4030_MODULE_INT 0x11
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#define TWL4030_MODULE_PM_MASTER 0x12
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#define TWL4030_MODULE_PM_RECEIVER 0x13
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#define TWL4030_MODULE_RTC 0x14
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#define TWL4030_MODULE_SECURED_REG 0x15
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/*
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* Read and write single 8-bit registers
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*/
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int twl4030_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
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int twl4030_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
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/*
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* Read and write several 8-bit registers at once.
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*
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* IMPORTANT: For twl4030_i2c_write(), allocate num_bytes + 1
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* for the value, and populate your data starting at offset 1.
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*/
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int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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/*----------------------------------------------------------------------*/
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/*
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* NOTE: at up to 1024 registers, this is a big chip.
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*
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* Avoid putting register declarations in this file, instead of into
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* a driver-private file, unless some of the registers in a block
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* need to be shared with other drivers. One example is blocks that
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* have Secondary IRQ Handler (SIH) registers.
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*/
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#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
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#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
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#define TWL4030_SIH_CTRL_COR_MASK BIT(2)
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/*----------------------------------------------------------------------*/
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/*
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* GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
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*/
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#define REG_GPIODATAIN1 0x0
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#define REG_GPIODATAIN2 0x1
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#define REG_GPIODATAIN3 0x2
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#define REG_GPIODATADIR1 0x3
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#define REG_GPIODATADIR2 0x4
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#define REG_GPIODATADIR3 0x5
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#define REG_GPIODATAOUT1 0x6
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#define REG_GPIODATAOUT2 0x7
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#define REG_GPIODATAOUT3 0x8
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#define REG_CLEARGPIODATAOUT1 0x9
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#define REG_CLEARGPIODATAOUT2 0xA
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#define REG_CLEARGPIODATAOUT3 0xB
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#define REG_SETGPIODATAOUT1 0xC
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#define REG_SETGPIODATAOUT2 0xD
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#define REG_SETGPIODATAOUT3 0xE
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#define REG_GPIO_DEBEN1 0xF
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#define REG_GPIO_DEBEN2 0x10
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#define REG_GPIO_DEBEN3 0x11
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#define REG_GPIO_CTRL 0x12
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#define REG_GPIOPUPDCTR1 0x13
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#define REG_GPIOPUPDCTR2 0x14
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#define REG_GPIOPUPDCTR3 0x15
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#define REG_GPIOPUPDCTR4 0x16
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#define REG_GPIOPUPDCTR5 0x17
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#define REG_GPIO_ISR1A 0x19
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#define REG_GPIO_ISR2A 0x1A
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#define REG_GPIO_ISR3A 0x1B
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#define REG_GPIO_IMR1A 0x1C
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#define REG_GPIO_IMR2A 0x1D
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#define REG_GPIO_IMR3A 0x1E
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#define REG_GPIO_ISR1B 0x1F
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#define REG_GPIO_ISR2B 0x20
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#define REG_GPIO_ISR3B 0x21
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#define REG_GPIO_IMR1B 0x22
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#define REG_GPIO_IMR2B 0x23
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#define REG_GPIO_IMR3B 0x24
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#define REG_GPIO_EDR1 0x28
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#define REG_GPIO_EDR2 0x29
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#define REG_GPIO_EDR3 0x2A
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#define REG_GPIO_EDR4 0x2B
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#define REG_GPIO_EDR5 0x2C
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#define REG_GPIO_SIH_CTRL 0x2D
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/* Up to 18 signals are available as GPIOs, when their
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* pins are not assigned to another use (such as ULPI/USB).
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*/
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#define TWL4030_GPIO_MAX 18
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/*----------------------------------------------------------------------*/
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/*
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* Keypad register offsets (use TWL4030_MODULE_KEYPAD)
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* ... SIH/interrupt only
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*/
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#define TWL4030_KEYPAD_KEYP_ISR1 0x11
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#define TWL4030_KEYPAD_KEYP_IMR1 0x12
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#define TWL4030_KEYPAD_KEYP_ISR2 0x13
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#define TWL4030_KEYPAD_KEYP_IMR2 0x14
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#define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
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#define TWL4030_KEYPAD_KEYP_EDR 0x16
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#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
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/*----------------------------------------------------------------------*/
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/*
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* Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
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* ... SIH/interrupt only
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*/
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#define TWL4030_MADC_ISR1 0x61
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#define TWL4030_MADC_IMR1 0x62
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#define TWL4030_MADC_ISR2 0x63
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#define TWL4030_MADC_IMR2 0x64
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#define TWL4030_MADC_SIR 0x65 /* test register */
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#define TWL4030_MADC_EDR 0x66
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#define TWL4030_MADC_SIH_CTRL 0x67
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/*----------------------------------------------------------------------*/
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/*
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* Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
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*/
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#define TWL4030_INTERRUPTS_BCIISR1A 0x0
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#define TWL4030_INTERRUPTS_BCIISR2A 0x1
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#define TWL4030_INTERRUPTS_BCIIMR1A 0x2
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#define TWL4030_INTERRUPTS_BCIIMR2A 0x3
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#define TWL4030_INTERRUPTS_BCIISR1B 0x4
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#define TWL4030_INTERRUPTS_BCIISR2B 0x5
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#define TWL4030_INTERRUPTS_BCIIMR1B 0x6
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#define TWL4030_INTERRUPTS_BCIIMR2B 0x7
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#define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
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#define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
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#define TWL4030_INTERRUPTS_BCIEDR1 0xa
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#define TWL4030_INTERRUPTS_BCIEDR2 0xb
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#define TWL4030_INTERRUPTS_BCIEDR3 0xc
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#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
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/*----------------------------------------------------------------------*/
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/*
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* Power Interrupt block register offsets (use TWL4030_MODULE_INT)
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*/
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#define TWL4030_INT_PWR_ISR1 0x0
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#define TWL4030_INT_PWR_IMR1 0x1
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#define TWL4030_INT_PWR_ISR2 0x2
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#define TWL4030_INT_PWR_IMR2 0x3
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#define TWL4030_INT_PWR_SIR 0x4 /* test register */
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#define TWL4030_INT_PWR_EDR1 0x5
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#define TWL4030_INT_PWR_EDR2 0x6
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#define TWL4030_INT_PWR_SIH_CTRL 0x7
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/*----------------------------------------------------------------------*/
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/* Power bus message definitions */
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/* The TWL4030/5030 splits its power-management resources (the various
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* regulators, clock and reset lines) into 3 processor groups - P1, P2 and
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* P3. These groups can then be configured to transition between sleep, wait-on
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* and active states by sending messages to the power bus. See Section 5.4.2
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* Power Resources of TWL4030 TRM
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*/
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/* Processor groups */
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#define DEV_GRP_NULL 0x0
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#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
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#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
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#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
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/* Resource groups */
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#define RES_GRP_RES 0x0 /* Reserved */
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#define RES_GRP_PP 0x1 /* Power providers */
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#define RES_GRP_RC 0x2 /* Reset and control */
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#define RES_GRP_PP_RC 0x3
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#define RES_GRP_PR 0x4 /* Power references */
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#define RES_GRP_PP_PR 0x5
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#define RES_GRP_RC_PR 0x6
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#define RES_GRP_ALL 0x7 /* All resource groups */
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#define RES_TYPE2_R0 0x0
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#define RES_TYPE_ALL 0x7
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#define RES_STATE_WRST 0xF
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#define RES_STATE_ACTIVE 0xE
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#define RES_STATE_SLEEP 0x8
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#define RES_STATE_OFF 0x0
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/* Power resources */
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/* Power providers */
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#define RES_VAUX1 1
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#define RES_VAUX2 2
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#define RES_VAUX3 3
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#define RES_VAUX4 4
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#define RES_VMMC1 5
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#define RES_VMMC2 6
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#define RES_VPLL1 7
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#define RES_VPLL2 8
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#define RES_VSIM 9
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#define RES_VDAC 10
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#define RES_VINTANA1 11
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#define RES_VINTANA2 12
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#define RES_VINTDIG 13
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#define RES_VIO 14
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#define RES_VDD1 15
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#define RES_VDD2 16
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#define RES_VUSB_1V5 17
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#define RES_VUSB_1V8 18
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#define RES_VUSB_3V1 19
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#define RES_VUSBCP 20
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#define RES_REGEN 21
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/* Reset and control */
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#define RES_NRES_PWRON 22
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#define RES_CLKEN 23
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#define RES_SYSEN 24
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#define RES_HFCLKOUT 25
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#define RES_32KCLKOUT 26
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#define RES_RESET 27
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/* Power Reference */
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#define RES_Main_Ref 28
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#define TOTAL_RESOURCES 28
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/*
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* Power Bus Message Format ... these can be sent individually by Linux,
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* but are usually part of downloaded scripts that are run when various
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* power events are triggered.
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*
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* Broadcast Message (16 Bits):
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* DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
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* RES_STATE[3:0]
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*
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* Singular Message (16 Bits):
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* DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
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*/
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#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
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( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
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| (type) << 4 | (state))
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#define MSG_SINGULAR(devgrp, id, state) \
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((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
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/*----------------------------------------------------------------------*/
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struct twl4030_bci_platform_data {
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int *battery_tmp_tbl;
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unsigned int tblsize;
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};
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/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
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struct twl4030_gpio_platform_data {
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int gpio_base;
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unsigned irq_base, irq_end;
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/* package the two LED signals as output-only GPIOs? */
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bool use_leds;
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/* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
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u8 mmc_cd;
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/* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
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u32 debounce;
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/* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
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* should be enabled. Else, if that bit is set in "pulldowns",
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* that pulldown is enabled. Don't waste power by letting any
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* digital inputs float...
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*/
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u32 pullups;
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u32 pulldowns;
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int (*setup)(struct device *dev,
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unsigned gpio, unsigned ngpio);
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int (*teardown)(struct device *dev,
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unsigned gpio, unsigned ngpio);
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};
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struct twl4030_madc_platform_data {
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int irq_line;
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};
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/* Boards have uniqe mappings of {row, col} --> keycode.
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* Column and row are 8 bits each, but range only from 0..7.
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* a PERSISTENT_KEY is "always on" and never reported.
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*/
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#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
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struct twl4030_keypad_data {
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const struct matrix_keymap_data *keymap_data;
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unsigned rows;
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unsigned cols;
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bool rep;
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};
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enum twl4030_usb_mode {
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T2_USB_MODE_ULPI = 1,
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T2_USB_MODE_CEA2011_3PIN = 2,
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};
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struct twl4030_usb_data {
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enum twl4030_usb_mode usb_mode;
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};
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struct twl4030_ins {
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u16 pmb_message;
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u8 delay;
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};
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struct twl4030_script {
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struct twl4030_ins *script;
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unsigned size;
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u8 flags;
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#define TWL4030_WRST_SCRIPT (1<<0)
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#define TWL4030_WAKEUP12_SCRIPT (1<<1)
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#define TWL4030_WAKEUP3_SCRIPT (1<<2)
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#define TWL4030_SLEEP_SCRIPT (1<<3)
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};
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struct twl4030_resconfig {
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u8 resource;
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u8 devgroup; /* Processor group that Power resource belongs to */
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u8 type; /* Power resource addressed, 6 / broadcast message */
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u8 type2; /* Power resource addressed, 3 / broadcast message */
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};
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struct twl4030_power_data {
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struct twl4030_script **scripts;
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unsigned num;
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struct twl4030_resconfig *resource_config;
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};
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extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
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struct twl4030_platform_data {
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unsigned irq_base, irq_end;
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struct twl4030_bci_platform_data *bci;
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struct twl4030_gpio_platform_data *gpio;
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struct twl4030_madc_platform_data *madc;
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struct twl4030_keypad_data *keypad;
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struct twl4030_usb_data *usb;
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struct twl4030_power_data *power;
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/* LDO regulators */
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struct regulator_init_data *vdac;
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struct regulator_init_data *vpll1;
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struct regulator_init_data *vpll2;
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struct regulator_init_data *vmmc1;
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struct regulator_init_data *vmmc2;
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struct regulator_init_data *vsim;
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struct regulator_init_data *vaux1;
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struct regulator_init_data *vaux2;
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struct regulator_init_data *vaux3;
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struct regulator_init_data *vaux4;
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/* REVISIT more to come ... _nothing_ should be hard-wired */
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};
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/*----------------------------------------------------------------------*/
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int twl4030_sih_setup(int module);
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/* Offsets to Power Registers */
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#define TWL4030_VDAC_DEV_GRP 0x3B
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#define TWL4030_VDAC_DEDICATED 0x3E
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#define TWL4030_VAUX1_DEV_GRP 0x17
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#define TWL4030_VAUX1_DEDICATED 0x1A
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#define TWL4030_VAUX2_DEV_GRP 0x1B
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#define TWL4030_VAUX2_DEDICATED 0x1E
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#define TWL4030_VAUX3_DEV_GRP 0x1F
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#define TWL4030_VAUX3_DEDICATED 0x22
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#if defined(CONFIG_TWL4030_BCI_BATTERY) || \
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defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
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extern int twl4030charger_usb_en(int enable);
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#else
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static inline int twl4030charger_usb_en(int enable) { return 0; }
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#endif
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/*----------------------------------------------------------------------*/
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/* Linux-specific regulator identifiers ... for now, we only support
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* the LDOs, and leave the three buck converters alone. VDD1 and VDD2
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* need to tie into hardware based voltage scaling (cpufreq etc), while
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* VIO is generally fixed.
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*/
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/* EXTERNAL dc-to-dc buck converters */
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#define TWL4030_REG_VDD1 0
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#define TWL4030_REG_VDD2 1
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#define TWL4030_REG_VIO 2
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/* EXTERNAL LDOs */
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#define TWL4030_REG_VDAC 3
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#define TWL4030_REG_VPLL1 4
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#define TWL4030_REG_VPLL2 5 /* not on all chips */
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#define TWL4030_REG_VMMC1 6
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#define TWL4030_REG_VMMC2 7 /* not on all chips */
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#define TWL4030_REG_VSIM 8 /* not on all chips */
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#define TWL4030_REG_VAUX1 9 /* not on all chips */
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#define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
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#define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
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#define TWL4030_REG_VAUX3 12 /* not on all chips */
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#define TWL4030_REG_VAUX4 13 /* not on all chips */
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/* INTERNAL LDOs */
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#define TWL4030_REG_VINTANA1 14
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#define TWL4030_REG_VINTANA2 15
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#define TWL4030_REG_VINTDIG 16
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#define TWL4030_REG_VUSB1V5 17
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#define TWL4030_REG_VUSB1V8 18
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#define TWL4030_REG_VUSB3V1 19
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#endif /* End of __TWL4030_H */
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