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As opposed to earlier incarnations, the memory controller on Tegra186 no longer implements an SMMU. Instead the SMMU is a regular ARM SMMU and in a separate IP block. However, the memory controller programs the SMMU stream IDs for each of the memory clients. Add a header file with definitions for each of these stream IDs and mark the #iommu-cells property as required on Tegra30 to Tegra210 in the device tree bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
119 lines
3.4 KiB
Plaintext
119 lines
3.4 KiB
Plaintext
NVIDIA Tegra Memory Controller device tree bindings
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===================================================
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memory-controller node
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----------------------
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Required properties:
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- compatible: Should be "nvidia,tegra<chip>-mc"
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- reg: Physical base address and length of the controller's registers.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- mc: the module's clock input
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- interrupts: The interrupt outputs from the controller.
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Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
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- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
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the SWGROUP of the master.
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This device implements an IOMMU that complies with the generic IOMMU binding.
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See ../iommu/iommu.txt for details.
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emc-timings subnode
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-------------------
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The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in
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register PMC_STRAPPING_OPT_A).
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Required properties for "emc-timings" nodes :
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- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.
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timing subnode
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--------------
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Each "emc-timings" node should contain a subnode for every supported EMC clock rate.
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Required properties for timing nodes :
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- clock-frequency : Should contain the memory clock rate in Hz.
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- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC
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(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be
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specified, according to the board documentation:
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MC_EMEM_ARB_CFG
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MC_EMEM_ARB_OUTSTANDING_REQ
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MC_EMEM_ARB_TIMING_RCD
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MC_EMEM_ARB_TIMING_RP
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MC_EMEM_ARB_TIMING_RC
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MC_EMEM_ARB_TIMING_RAS
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MC_EMEM_ARB_TIMING_FAW
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MC_EMEM_ARB_TIMING_RRD
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MC_EMEM_ARB_TIMING_RAP2PRE
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MC_EMEM_ARB_TIMING_WAP2PRE
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MC_EMEM_ARB_TIMING_R2R
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MC_EMEM_ARB_TIMING_W2W
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MC_EMEM_ARB_TIMING_R2W
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MC_EMEM_ARB_TIMING_W2R
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MC_EMEM_ARB_DA_TURNS
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MC_EMEM_ARB_DA_COVERS
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MC_EMEM_ARB_MISC0
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MC_EMEM_ARB_MISC1
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MC_EMEM_ARB_RING1_THROTTLE
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Example SoC include file:
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/ {
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mc: memory-controller@70019000 {
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compatible = "nvidia,tegra124-mc";
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reg = <0x0 0x70019000 0x0 0x1000>;
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clocks = <&tegra_car TEGRA124_CLK_MC>;
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clock-names = "mc";
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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};
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sdhci@700b0000 {
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compatible = "nvidia,tegra124-sdhci";
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...
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iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
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};
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};
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Example board file:
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/ {
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memory-controller@70019000 {
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emc-timings-3 {
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nvidia,ram-code = <3>;
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timing-12750000 {
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clock-frequency = <12750000>;
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nvidia,emem-configuration = <
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0x40040001 /* MC_EMEM_ARB_CFG */
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0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
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0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
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0x00000001 /* MC_EMEM_ARB_TIMING_RP */
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0x00000002 /* MC_EMEM_ARB_TIMING_RC */
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0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
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0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
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0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
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0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
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0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
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0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
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0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
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0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
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0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
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0x06030203 /* MC_EMEM_ARB_DA_TURNS */
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0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
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0x77e30303 /* MC_EMEM_ARB_MISC0 */
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0x70000f03 /* MC_EMEM_ARB_MISC1 */
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0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
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>;
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};
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};
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};
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};
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