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87e609760b
Replace __init by __devinit. Warning message: WARNING: vmlinux.o(.data+0xbc14): Section mismatch in reference from the variable temac_of_driver to the function .init.text:temac_of_probe() The variable temac_of_driver references the function __init temac_of_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console, Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: David S. Miller <davem@davemloft.net>
1151 lines
29 KiB
C
1151 lines
29 KiB
C
/*
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* Driver for Xilinx TEMAC Ethernet device
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*
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* Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
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* Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
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* Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
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*
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* This is a driver for the Xilinx ll_temac ipcore which is often used
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* in the Virtex and Spartan series of chips.
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*
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* Notes:
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* - The ll_temac hardware uses indirect access for many of the TEMAC
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* registers, include the MDIO bus. However, indirect access to MDIO
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* registers take considerably more clock cycles than to TEMAC registers.
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* MDIO accesses are long, so threads doing them should probably sleep
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* rather than busywait. However, since only one indirect access can be
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* in progress at any given time, that means that *all* indirect accesses
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* could end up sleeping (to wait for an MDIO access to complete).
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* Fortunately none of the indirect accesses are on the 'hot' path for tx
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* or rx, so this should be okay.
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*
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* TODO:
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* - Factor out locallink DMA code into separate driver
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* - Fix multicast assignment.
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* - Fix support for hardware checksumming.
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* - Testing. Lots and lots of testing.
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*
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*/
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/netdevice.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_mdio.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
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#include <linux/udp.h> /* needed for sizeof(udphdr) */
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#include <linux/phy.h>
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#include <linux/in.h>
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#include <linux/io.h>
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#include <linux/ip.h>
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#include <linux/slab.h>
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#include "ll_temac.h"
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#define TX_BD_NUM 64
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#define RX_BD_NUM 128
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/* ---------------------------------------------------------------------
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* Low level register access functions
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*/
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u32 temac_ior(struct temac_local *lp, int offset)
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{
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return in_be32((u32 *)(lp->regs + offset));
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}
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void temac_iow(struct temac_local *lp, int offset, u32 value)
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{
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out_be32((u32 *) (lp->regs + offset), value);
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}
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int temac_indirect_busywait(struct temac_local *lp)
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{
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long end = jiffies + 2;
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while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
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if (end - jiffies <= 0) {
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WARN_ON(1);
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return -ETIMEDOUT;
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}
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msleep(1);
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}
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return 0;
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}
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/**
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* temac_indirect_in32
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*
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* lp->indirect_mutex must be held when calling this function
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*/
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u32 temac_indirect_in32(struct temac_local *lp, int reg)
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{
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u32 val;
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if (temac_indirect_busywait(lp))
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return -ETIMEDOUT;
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temac_iow(lp, XTE_CTL0_OFFSET, reg);
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if (temac_indirect_busywait(lp))
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return -ETIMEDOUT;
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val = temac_ior(lp, XTE_LSW0_OFFSET);
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return val;
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}
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/**
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* temac_indirect_out32
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*
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* lp->indirect_mutex must be held when calling this function
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*/
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void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
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{
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if (temac_indirect_busywait(lp))
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return;
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temac_iow(lp, XTE_LSW0_OFFSET, value);
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temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
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}
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/**
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* temac_dma_in32 - Memory mapped DMA read, this function expects a
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* register input that is based on DCR word addresses which
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* are then converted to memory mapped byte addresses
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*/
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static u32 temac_dma_in32(struct temac_local *lp, int reg)
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{
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return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
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}
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/**
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* temac_dma_out32 - Memory mapped DMA read, this function expects a
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* register input that is based on DCR word addresses which
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* are then converted to memory mapped byte addresses
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*/
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static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
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{
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out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
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}
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/* DMA register access functions can be DCR based or memory mapped.
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* The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
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* memory mapped.
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*/
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#ifdef CONFIG_PPC_DCR
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/**
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* temac_dma_dcr_in32 - DCR based DMA read
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*/
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static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
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{
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return dcr_read(lp->sdma_dcrs, reg);
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}
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/**
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* temac_dma_dcr_out32 - DCR based DMA write
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*/
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static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
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{
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dcr_write(lp->sdma_dcrs, reg, value);
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}
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/**
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* temac_dcr_setup - If the DMA is DCR based, then setup the address and
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* I/O functions
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*/
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static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
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struct device_node *np)
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{
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unsigned int dcrs;
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/* setup the dcr address mapping if it's in the device tree */
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dcrs = dcr_resource_start(np, 0);
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if (dcrs != 0) {
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lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
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lp->dma_in = temac_dma_dcr_in;
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lp->dma_out = temac_dma_dcr_out;
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dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
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return 0;
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}
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/* no DCR in the device tree, indicate a failure */
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return -1;
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}
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#else
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/*
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* temac_dcr_setup - This is a stub for when DCR is not supported,
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* such as with MicroBlaze
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*/
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static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
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struct device_node *np)
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{
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return -1;
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}
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#endif
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/**
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* * temac_dma_bd_release - Release buffer descriptor rings
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*/
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static void temac_dma_bd_release(struct net_device *ndev)
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{
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struct temac_local *lp = netdev_priv(ndev);
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int i;
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for (i = 0; i < RX_BD_NUM; i++) {
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if (!lp->rx_skb[i])
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break;
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else {
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dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
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XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
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dev_kfree_skb(lp->rx_skb[i]);
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}
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}
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if (lp->rx_bd_v)
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dma_free_coherent(ndev->dev.parent,
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sizeof(*lp->rx_bd_v) * RX_BD_NUM,
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lp->rx_bd_v, lp->rx_bd_p);
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if (lp->tx_bd_v)
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dma_free_coherent(ndev->dev.parent,
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sizeof(*lp->tx_bd_v) * TX_BD_NUM,
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lp->tx_bd_v, lp->tx_bd_p);
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if (lp->rx_skb)
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kfree(lp->rx_skb);
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}
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/**
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* temac_dma_bd_init - Setup buffer descriptor rings
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*/
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static int temac_dma_bd_init(struct net_device *ndev)
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{
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struct temac_local *lp = netdev_priv(ndev);
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struct sk_buff *skb;
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int i;
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lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
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if (!lp->rx_skb) {
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dev_err(&ndev->dev,
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"can't allocate memory for DMA RX buffer\n");
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goto out;
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}
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/* allocate the tx and rx ring buffer descriptors. */
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/* returns a virtual addres and a physical address. */
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lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
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sizeof(*lp->tx_bd_v) * TX_BD_NUM,
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&lp->tx_bd_p, GFP_KERNEL);
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if (!lp->tx_bd_v) {
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dev_err(&ndev->dev,
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"unable to allocate DMA TX buffer descriptors");
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goto out;
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}
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lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
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sizeof(*lp->rx_bd_v) * RX_BD_NUM,
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&lp->rx_bd_p, GFP_KERNEL);
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if (!lp->rx_bd_v) {
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dev_err(&ndev->dev,
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"unable to allocate DMA RX buffer descriptors");
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goto out;
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}
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memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
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for (i = 0; i < TX_BD_NUM; i++) {
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lp->tx_bd_v[i].next = lp->tx_bd_p +
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sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
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}
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memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
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for (i = 0; i < RX_BD_NUM; i++) {
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lp->rx_bd_v[i].next = lp->rx_bd_p +
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sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
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skb = netdev_alloc_skb_ip_align(ndev,
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XTE_MAX_JUMBO_FRAME_SIZE);
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if (skb == 0) {
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dev_err(&ndev->dev, "alloc_skb error %d\n", i);
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goto out;
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}
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lp->rx_skb[i] = skb;
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/* returns physical address of skb->data */
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lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
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skb->data,
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XTE_MAX_JUMBO_FRAME_SIZE,
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DMA_FROM_DEVICE);
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lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
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lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
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}
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lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
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CHNL_CTRL_IRQ_EN |
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CHNL_CTRL_IRQ_DLY_EN |
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CHNL_CTRL_IRQ_COAL_EN);
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/* 0x10220483 */
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/* 0x00100483 */
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lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
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CHNL_CTRL_IRQ_EN |
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CHNL_CTRL_IRQ_DLY_EN |
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CHNL_CTRL_IRQ_COAL_EN |
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CHNL_CTRL_IRQ_IOE);
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/* 0xff010283 */
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lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
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lp->dma_out(lp, RX_TAILDESC_PTR,
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lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
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lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
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return 0;
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out:
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temac_dma_bd_release(ndev);
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return -ENOMEM;
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}
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/* ---------------------------------------------------------------------
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* net_device_ops
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*/
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static int temac_set_mac_address(struct net_device *ndev, void *address)
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{
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struct temac_local *lp = netdev_priv(ndev);
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if (address)
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memcpy(ndev->dev_addr, address, ETH_ALEN);
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if (!is_valid_ether_addr(ndev->dev_addr))
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random_ether_addr(ndev->dev_addr);
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/* set up unicast MAC address filter set its mac address */
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mutex_lock(&lp->indirect_mutex);
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temac_indirect_out32(lp, XTE_UAW0_OFFSET,
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(ndev->dev_addr[0]) |
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(ndev->dev_addr[1] << 8) |
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(ndev->dev_addr[2] << 16) |
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(ndev->dev_addr[3] << 24));
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/* There are reserved bits in EUAW1
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* so don't affect them Set MAC bits [47:32] in EUAW1 */
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temac_indirect_out32(lp, XTE_UAW1_OFFSET,
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(ndev->dev_addr[4] & 0x000000ff) |
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(ndev->dev_addr[5] << 8));
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mutex_unlock(&lp->indirect_mutex);
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return 0;
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}
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static int netdev_set_mac_address(struct net_device *ndev, void *p)
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{
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struct sockaddr *addr = p;
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return temac_set_mac_address(ndev, addr->sa_data);
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}
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static void temac_set_multicast_list(struct net_device *ndev)
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{
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struct temac_local *lp = netdev_priv(ndev);
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u32 multi_addr_msw, multi_addr_lsw, val;
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int i;
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mutex_lock(&lp->indirect_mutex);
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if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
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netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
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/*
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* We must make the kernel realise we had to move
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* into promisc mode or we start all out war on
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* the cable. If it was a promisc request the
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* flag is already set. If not we assert it.
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*/
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ndev->flags |= IFF_PROMISC;
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temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
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dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
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} else if (!netdev_mc_empty(ndev)) {
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struct netdev_hw_addr *ha;
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i = 0;
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netdev_for_each_mc_addr(ha, ndev) {
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if (i >= MULTICAST_CAM_TABLE_NUM)
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break;
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multi_addr_msw = ((ha->addr[3] << 24) |
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(ha->addr[2] << 16) |
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(ha->addr[1] << 8) |
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(ha->addr[0]));
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temac_indirect_out32(lp, XTE_MAW0_OFFSET,
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multi_addr_msw);
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multi_addr_lsw = ((ha->addr[5] << 8) |
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(ha->addr[4]) | (i << 16));
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temac_indirect_out32(lp, XTE_MAW1_OFFSET,
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multi_addr_lsw);
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i++;
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}
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} else {
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val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
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temac_indirect_out32(lp, XTE_AFM_OFFSET,
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val & ~XTE_AFM_EPPRM_MASK);
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temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
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temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
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dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
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}
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mutex_unlock(&lp->indirect_mutex);
|
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}
|
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|
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struct temac_option {
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int flg;
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u32 opt;
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u32 reg;
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u32 m_or;
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u32 m_and;
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} temac_options[] = {
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/* Turn on jumbo packet support for both Rx and Tx */
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{
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.opt = XTE_OPTION_JUMBO,
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.reg = XTE_TXC_OFFSET,
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.m_or = XTE_TXC_TXJMBO_MASK,
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},
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{
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.opt = XTE_OPTION_JUMBO,
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.reg = XTE_RXC1_OFFSET,
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.m_or =XTE_RXC1_RXJMBO_MASK,
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},
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/* Turn on VLAN packet support for both Rx and Tx */
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{
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.opt = XTE_OPTION_VLAN,
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.reg = XTE_TXC_OFFSET,
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.m_or =XTE_TXC_TXVLAN_MASK,
|
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},
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{
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.opt = XTE_OPTION_VLAN,
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.reg = XTE_RXC1_OFFSET,
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.m_or =XTE_RXC1_RXVLAN_MASK,
|
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},
|
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/* Turn on FCS stripping on receive packets */
|
|
{
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.opt = XTE_OPTION_FCS_STRIP,
|
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.reg = XTE_RXC1_OFFSET,
|
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.m_or =XTE_RXC1_RXFCS_MASK,
|
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},
|
|
/* Turn on FCS insertion on transmit packets */
|
|
{
|
|
.opt = XTE_OPTION_FCS_INSERT,
|
|
.reg = XTE_TXC_OFFSET,
|
|
.m_or =XTE_TXC_TXFCS_MASK,
|
|
},
|
|
/* Turn on length/type field checking on receive packets */
|
|
{
|
|
.opt = XTE_OPTION_LENTYPE_ERR,
|
|
.reg = XTE_RXC1_OFFSET,
|
|
.m_or =XTE_RXC1_RXLT_MASK,
|
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},
|
|
/* Turn on flow control */
|
|
{
|
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.opt = XTE_OPTION_FLOW_CONTROL,
|
|
.reg = XTE_FCC_OFFSET,
|
|
.m_or =XTE_FCC_RXFLO_MASK,
|
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},
|
|
/* Turn on flow control */
|
|
{
|
|
.opt = XTE_OPTION_FLOW_CONTROL,
|
|
.reg = XTE_FCC_OFFSET,
|
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.m_or =XTE_FCC_TXFLO_MASK,
|
|
},
|
|
/* Turn on promiscuous frame filtering (all frames are received ) */
|
|
{
|
|
.opt = XTE_OPTION_PROMISC,
|
|
.reg = XTE_AFM_OFFSET,
|
|
.m_or =XTE_AFM_EPPRM_MASK,
|
|
},
|
|
/* Enable transmitter if not already enabled */
|
|
{
|
|
.opt = XTE_OPTION_TXEN,
|
|
.reg = XTE_TXC_OFFSET,
|
|
.m_or =XTE_TXC_TXEN_MASK,
|
|
},
|
|
/* Enable receiver? */
|
|
{
|
|
.opt = XTE_OPTION_RXEN,
|
|
.reg = XTE_RXC1_OFFSET,
|
|
.m_or =XTE_RXC1_RXEN_MASK,
|
|
},
|
|
{}
|
|
};
|
|
|
|
/**
|
|
* temac_setoptions
|
|
*/
|
|
static u32 temac_setoptions(struct net_device *ndev, u32 options)
|
|
{
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
struct temac_option *tp = &temac_options[0];
|
|
int reg;
|
|
|
|
mutex_lock(&lp->indirect_mutex);
|
|
while (tp->opt) {
|
|
reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
|
|
if (options & tp->opt)
|
|
reg |= tp->m_or;
|
|
temac_indirect_out32(lp, tp->reg, reg);
|
|
tp++;
|
|
}
|
|
lp->options |= options;
|
|
mutex_unlock(&lp->indirect_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Initialize temac */
|
|
static void temac_device_reset(struct net_device *ndev)
|
|
{
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
u32 timeout;
|
|
u32 val;
|
|
|
|
/* Perform a software reset */
|
|
|
|
/* 0x300 host enable bit ? */
|
|
/* reset PHY through control register ?:1 */
|
|
|
|
dev_dbg(&ndev->dev, "%s()\n", __func__);
|
|
|
|
mutex_lock(&lp->indirect_mutex);
|
|
/* Reset the receiver and wait for it to finish reset */
|
|
temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
|
|
timeout = 1000;
|
|
while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
|
|
udelay(1);
|
|
if (--timeout == 0) {
|
|
dev_err(&ndev->dev,
|
|
"temac_device_reset RX reset timeout!!\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Reset the transmitter and wait for it to finish reset */
|
|
temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
|
|
timeout = 1000;
|
|
while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
|
|
udelay(1);
|
|
if (--timeout == 0) {
|
|
dev_err(&ndev->dev,
|
|
"temac_device_reset TX reset timeout!!\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Disable the receiver */
|
|
val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
|
|
temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
|
|
|
|
/* Reset Local Link (DMA) */
|
|
lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
|
|
timeout = 1000;
|
|
while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
|
|
udelay(1);
|
|
if (--timeout == 0) {
|
|
dev_err(&ndev->dev,
|
|
"temac_device_reset DMA reset timeout!!\n");
|
|
break;
|
|
}
|
|
}
|
|
lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
|
|
|
|
if (temac_dma_bd_init(ndev)) {
|
|
dev_err(&ndev->dev,
|
|
"temac_device_reset descriptor allocation failed\n");
|
|
}
|
|
|
|
temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
|
|
temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
|
|
temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
|
|
temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
|
|
|
|
mutex_unlock(&lp->indirect_mutex);
|
|
|
|
/* Sync default options with HW
|
|
* but leave receiver and transmitter disabled. */
|
|
temac_setoptions(ndev,
|
|
lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
|
|
|
|
temac_set_mac_address(ndev, NULL);
|
|
|
|
/* Set address filter table */
|
|
temac_set_multicast_list(ndev);
|
|
if (temac_setoptions(ndev, lp->options))
|
|
dev_err(&ndev->dev, "Error setting TEMAC options\n");
|
|
|
|
/* Init Driver variable */
|
|
ndev->trans_start = jiffies; /* prevent tx timeout */
|
|
}
|
|
|
|
void temac_adjust_link(struct net_device *ndev)
|
|
{
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
struct phy_device *phy = lp->phy_dev;
|
|
u32 mii_speed;
|
|
int link_state;
|
|
|
|
/* hash together the state values to decide if something has changed */
|
|
link_state = phy->speed | (phy->duplex << 1) | phy->link;
|
|
|
|
mutex_lock(&lp->indirect_mutex);
|
|
if (lp->last_link != link_state) {
|
|
mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
|
|
mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
|
|
|
|
switch (phy->speed) {
|
|
case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
|
|
case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
|
|
case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
|
|
}
|
|
|
|
/* Write new speed setting out to TEMAC */
|
|
temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
|
|
lp->last_link = link_state;
|
|
phy_print_status(phy);
|
|
}
|
|
mutex_unlock(&lp->indirect_mutex);
|
|
}
|
|
|
|
static void temac_start_xmit_done(struct net_device *ndev)
|
|
{
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
struct cdmac_bd *cur_p;
|
|
unsigned int stat = 0;
|
|
|
|
cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
|
|
stat = cur_p->app0;
|
|
|
|
while (stat & STS_CTRL_APP0_CMPLT) {
|
|
dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
|
|
DMA_TO_DEVICE);
|
|
if (cur_p->app4)
|
|
dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
|
|
cur_p->app0 = 0;
|
|
cur_p->app1 = 0;
|
|
cur_p->app2 = 0;
|
|
cur_p->app3 = 0;
|
|
cur_p->app4 = 0;
|
|
|
|
ndev->stats.tx_packets++;
|
|
ndev->stats.tx_bytes += cur_p->len;
|
|
|
|
lp->tx_bd_ci++;
|
|
if (lp->tx_bd_ci >= TX_BD_NUM)
|
|
lp->tx_bd_ci = 0;
|
|
|
|
cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
|
|
stat = cur_p->app0;
|
|
}
|
|
|
|
netif_wake_queue(ndev);
|
|
}
|
|
|
|
static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
|
|
{
|
|
struct cdmac_bd *cur_p;
|
|
int tail;
|
|
|
|
tail = lp->tx_bd_tail;
|
|
cur_p = &lp->tx_bd_v[tail];
|
|
|
|
do {
|
|
if (cur_p->app0)
|
|
return NETDEV_TX_BUSY;
|
|
|
|
tail++;
|
|
if (tail >= TX_BD_NUM)
|
|
tail = 0;
|
|
|
|
cur_p = &lp->tx_bd_v[tail];
|
|
num_frag--;
|
|
} while (num_frag >= 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
|
|
{
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
struct cdmac_bd *cur_p;
|
|
dma_addr_t start_p, tail_p;
|
|
int ii;
|
|
unsigned long num_frag;
|
|
skb_frag_t *frag;
|
|
|
|
num_frag = skb_shinfo(skb)->nr_frags;
|
|
frag = &skb_shinfo(skb)->frags[0];
|
|
start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
|
|
cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
|
|
|
|
if (temac_check_tx_bd_space(lp, num_frag)) {
|
|
if (!netif_queue_stopped(ndev)) {
|
|
netif_stop_queue(ndev);
|
|
return NETDEV_TX_BUSY;
|
|
}
|
|
return NETDEV_TX_BUSY;
|
|
}
|
|
|
|
cur_p->app0 = 0;
|
|
if (skb->ip_summed == CHECKSUM_PARTIAL) {
|
|
unsigned int csum_start_off = skb_checksum_start_offset(skb);
|
|
unsigned int csum_index_off = csum_start_off + skb->csum_offset;
|
|
|
|
cur_p->app0 |= 1; /* TX Checksum Enabled */
|
|
cur_p->app1 = (csum_start_off << 16) | csum_index_off;
|
|
cur_p->app2 = 0; /* initial checksum seed */
|
|
}
|
|
|
|
cur_p->app0 |= STS_CTRL_APP0_SOP;
|
|
cur_p->len = skb_headlen(skb);
|
|
cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
|
|
DMA_TO_DEVICE);
|
|
cur_p->app4 = (unsigned long)skb;
|
|
|
|
for (ii = 0; ii < num_frag; ii++) {
|
|
lp->tx_bd_tail++;
|
|
if (lp->tx_bd_tail >= TX_BD_NUM)
|
|
lp->tx_bd_tail = 0;
|
|
|
|
cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
|
|
cur_p->phys = dma_map_single(ndev->dev.parent,
|
|
(void *)page_address(frag->page) +
|
|
frag->page_offset,
|
|
frag->size, DMA_TO_DEVICE);
|
|
cur_p->len = frag->size;
|
|
cur_p->app0 = 0;
|
|
frag++;
|
|
}
|
|
cur_p->app0 |= STS_CTRL_APP0_EOP;
|
|
|
|
tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
|
|
lp->tx_bd_tail++;
|
|
if (lp->tx_bd_tail >= TX_BD_NUM)
|
|
lp->tx_bd_tail = 0;
|
|
|
|
/* Kick off the transfer */
|
|
lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
|
|
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
|
|
static void ll_temac_recv(struct net_device *ndev)
|
|
{
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
struct sk_buff *skb, *new_skb;
|
|
unsigned int bdstat;
|
|
struct cdmac_bd *cur_p;
|
|
dma_addr_t tail_p;
|
|
int length;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&lp->rx_lock, flags);
|
|
|
|
tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
|
|
cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
|
|
|
|
bdstat = cur_p->app0;
|
|
while ((bdstat & STS_CTRL_APP0_CMPLT)) {
|
|
|
|
skb = lp->rx_skb[lp->rx_bd_ci];
|
|
length = cur_p->app4 & 0x3FFF;
|
|
|
|
dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
|
|
DMA_FROM_DEVICE);
|
|
|
|
skb_put(skb, length);
|
|
skb->dev = ndev;
|
|
skb->protocol = eth_type_trans(skb, ndev);
|
|
skb_checksum_none_assert(skb);
|
|
|
|
/* if we're doing rx csum offload, set it up */
|
|
if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
|
|
(skb->protocol == __constant_htons(ETH_P_IP)) &&
|
|
(skb->len > 64)) {
|
|
|
|
skb->csum = cur_p->app3 & 0xFFFF;
|
|
skb->ip_summed = CHECKSUM_COMPLETE;
|
|
}
|
|
|
|
netif_rx(skb);
|
|
|
|
ndev->stats.rx_packets++;
|
|
ndev->stats.rx_bytes += length;
|
|
|
|
new_skb = netdev_alloc_skb_ip_align(ndev,
|
|
XTE_MAX_JUMBO_FRAME_SIZE);
|
|
|
|
if (new_skb == 0) {
|
|
dev_err(&ndev->dev, "no memory for new sk_buff\n");
|
|
spin_unlock_irqrestore(&lp->rx_lock, flags);
|
|
return;
|
|
}
|
|
|
|
cur_p->app0 = STS_CTRL_APP0_IRQONEND;
|
|
cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
|
|
XTE_MAX_JUMBO_FRAME_SIZE,
|
|
DMA_FROM_DEVICE);
|
|
cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
|
|
lp->rx_skb[lp->rx_bd_ci] = new_skb;
|
|
|
|
lp->rx_bd_ci++;
|
|
if (lp->rx_bd_ci >= RX_BD_NUM)
|
|
lp->rx_bd_ci = 0;
|
|
|
|
cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
|
|
bdstat = cur_p->app0;
|
|
}
|
|
lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
|
|
|
|
spin_unlock_irqrestore(&lp->rx_lock, flags);
|
|
}
|
|
|
|
static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
|
|
{
|
|
struct net_device *ndev = _ndev;
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
unsigned int status;
|
|
|
|
status = lp->dma_in(lp, TX_IRQ_REG);
|
|
lp->dma_out(lp, TX_IRQ_REG, status);
|
|
|
|
if (status & (IRQ_COAL | IRQ_DLY))
|
|
temac_start_xmit_done(lp->ndev);
|
|
if (status & 0x080)
|
|
dev_err(&ndev->dev, "DMA error 0x%x\n", status);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
|
|
{
|
|
struct net_device *ndev = _ndev;
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
unsigned int status;
|
|
|
|
/* Read and clear the status registers */
|
|
status = lp->dma_in(lp, RX_IRQ_REG);
|
|
lp->dma_out(lp, RX_IRQ_REG, status);
|
|
|
|
if (status & (IRQ_COAL | IRQ_DLY))
|
|
ll_temac_recv(lp->ndev);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int temac_open(struct net_device *ndev)
|
|
{
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
int rc;
|
|
|
|
dev_dbg(&ndev->dev, "temac_open()\n");
|
|
|
|
if (lp->phy_node) {
|
|
lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
|
|
temac_adjust_link, 0, 0);
|
|
if (!lp->phy_dev) {
|
|
dev_err(lp->dev, "of_phy_connect() failed\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
phy_start(lp->phy_dev);
|
|
}
|
|
|
|
rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
|
|
if (rc)
|
|
goto err_tx_irq;
|
|
rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
|
|
if (rc)
|
|
goto err_rx_irq;
|
|
|
|
temac_device_reset(ndev);
|
|
return 0;
|
|
|
|
err_rx_irq:
|
|
free_irq(lp->tx_irq, ndev);
|
|
err_tx_irq:
|
|
if (lp->phy_dev)
|
|
phy_disconnect(lp->phy_dev);
|
|
lp->phy_dev = NULL;
|
|
dev_err(lp->dev, "request_irq() failed\n");
|
|
return rc;
|
|
}
|
|
|
|
static int temac_stop(struct net_device *ndev)
|
|
{
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
|
|
dev_dbg(&ndev->dev, "temac_close()\n");
|
|
|
|
free_irq(lp->tx_irq, ndev);
|
|
free_irq(lp->rx_irq, ndev);
|
|
|
|
if (lp->phy_dev)
|
|
phy_disconnect(lp->phy_dev);
|
|
lp->phy_dev = NULL;
|
|
|
|
temac_dma_bd_release(ndev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
static void
|
|
temac_poll_controller(struct net_device *ndev)
|
|
{
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
|
|
disable_irq(lp->tx_irq);
|
|
disable_irq(lp->rx_irq);
|
|
|
|
ll_temac_rx_irq(lp->tx_irq, ndev);
|
|
ll_temac_tx_irq(lp->rx_irq, ndev);
|
|
|
|
enable_irq(lp->tx_irq);
|
|
enable_irq(lp->rx_irq);
|
|
}
|
|
#endif
|
|
|
|
static const struct net_device_ops temac_netdev_ops = {
|
|
.ndo_open = temac_open,
|
|
.ndo_stop = temac_stop,
|
|
.ndo_start_xmit = temac_start_xmit,
|
|
.ndo_set_mac_address = netdev_set_mac_address,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
//.ndo_set_multicast_list = temac_set_multicast_list,
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
.ndo_poll_controller = temac_poll_controller,
|
|
#endif
|
|
};
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* SYSFS device attributes
|
|
*/
|
|
static ssize_t temac_show_llink_regs(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
struct net_device *ndev = dev_get_drvdata(dev);
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
int i, len = 0;
|
|
|
|
for (i = 0; i < 0x11; i++)
|
|
len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
|
|
(i % 8) == 7 ? "\n" : " ");
|
|
len += sprintf(buf + len, "\n");
|
|
|
|
return len;
|
|
}
|
|
|
|
static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
|
|
|
|
static struct attribute *temac_device_attrs[] = {
|
|
&dev_attr_llink_regs.attr,
|
|
NULL,
|
|
};
|
|
|
|
static const struct attribute_group temac_attr_group = {
|
|
.attrs = temac_device_attrs,
|
|
};
|
|
|
|
static int __devinit
|
|
temac_of_probe(struct platform_device *op, const struct of_device_id *match)
|
|
{
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|
struct device_node *np;
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struct temac_local *lp;
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|
struct net_device *ndev;
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|
const void *addr;
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|
__be32 *p;
|
|
int size, rc = 0;
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|
|
|
/* Init network device structure */
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ndev = alloc_etherdev(sizeof(*lp));
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|
if (!ndev) {
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|
dev_err(&op->dev, "could not allocate device.\n");
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|
return -ENOMEM;
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|
}
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|
ether_setup(ndev);
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|
dev_set_drvdata(&op->dev, ndev);
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|
SET_NETDEV_DEV(ndev, &op->dev);
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ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
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ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
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ndev->netdev_ops = &temac_netdev_ops;
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#if 0
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ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
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ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
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ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
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ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
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ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
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ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
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ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
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ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
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ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
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ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
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ndev->features |= NETIF_F_LRO; /* large receive offload */
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#endif
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|
|
|
/* setup temac private info structure */
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lp = netdev_priv(ndev);
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lp->ndev = ndev;
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|
lp->dev = &op->dev;
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lp->options = XTE_OPTION_DEFAULTS;
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|
spin_lock_init(&lp->rx_lock);
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|
mutex_init(&lp->indirect_mutex);
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|
|
|
/* map device registers */
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lp->regs = of_iomap(op->dev.of_node, 0);
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|
if (!lp->regs) {
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dev_err(&op->dev, "could not map temac regs.\n");
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|
goto nodev;
|
|
}
|
|
|
|
/* Setup checksum offload, but default to off if not specified */
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|
lp->temac_features = 0;
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p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
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if (p && be32_to_cpu(*p)) {
|
|
lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
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|
/* Can checksum TCP/UDP over IPv4. */
|
|
ndev->features |= NETIF_F_IP_CSUM;
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|
}
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|
p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
|
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if (p && be32_to_cpu(*p))
|
|
lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
|
|
|
|
/* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
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np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
|
|
if (!np) {
|
|
dev_err(&op->dev, "could not find DMA node\n");
|
|
goto err_iounmap;
|
|
}
|
|
|
|
/* Setup the DMA register accesses, could be DCR or memory mapped */
|
|
if (temac_dcr_setup(lp, op, np)) {
|
|
|
|
/* no DCR in the device tree, try non-DCR */
|
|
lp->sdma_regs = of_iomap(np, 0);
|
|
if (lp->sdma_regs) {
|
|
lp->dma_in = temac_dma_in32;
|
|
lp->dma_out = temac_dma_out32;
|
|
dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
|
|
} else {
|
|
dev_err(&op->dev, "unable to map DMA registers\n");
|
|
of_node_put(np);
|
|
goto err_iounmap;
|
|
}
|
|
}
|
|
|
|
lp->rx_irq = irq_of_parse_and_map(np, 0);
|
|
lp->tx_irq = irq_of_parse_and_map(np, 1);
|
|
|
|
of_node_put(np); /* Finished with the DMA node; drop the reference */
|
|
|
|
if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
|
|
dev_err(&op->dev, "could not determine irqs\n");
|
|
rc = -ENOMEM;
|
|
goto err_iounmap_2;
|
|
}
|
|
|
|
|
|
/* Retrieve the MAC address */
|
|
addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
|
|
if ((!addr) || (size != 6)) {
|
|
dev_err(&op->dev, "could not find MAC address\n");
|
|
rc = -ENODEV;
|
|
goto err_iounmap_2;
|
|
}
|
|
temac_set_mac_address(ndev, (void *)addr);
|
|
|
|
rc = temac_mdio_setup(lp, op->dev.of_node);
|
|
if (rc)
|
|
dev_warn(&op->dev, "error registering MDIO bus\n");
|
|
|
|
lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
|
|
if (lp->phy_node)
|
|
dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
|
|
|
|
/* Add the device attributes */
|
|
rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
|
|
if (rc) {
|
|
dev_err(lp->dev, "Error creating sysfs files\n");
|
|
goto err_iounmap_2;
|
|
}
|
|
|
|
rc = register_netdev(lp->ndev);
|
|
if (rc) {
|
|
dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
|
|
goto err_register_ndev;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_register_ndev:
|
|
sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
|
|
err_iounmap_2:
|
|
if (lp->sdma_regs)
|
|
iounmap(lp->sdma_regs);
|
|
err_iounmap:
|
|
iounmap(lp->regs);
|
|
nodev:
|
|
free_netdev(ndev);
|
|
ndev = NULL;
|
|
return rc;
|
|
}
|
|
|
|
static int __devexit temac_of_remove(struct platform_device *op)
|
|
{
|
|
struct net_device *ndev = dev_get_drvdata(&op->dev);
|
|
struct temac_local *lp = netdev_priv(ndev);
|
|
|
|
temac_mdio_teardown(lp);
|
|
unregister_netdev(ndev);
|
|
sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
|
|
if (lp->phy_node)
|
|
of_node_put(lp->phy_node);
|
|
lp->phy_node = NULL;
|
|
dev_set_drvdata(&op->dev, NULL);
|
|
iounmap(lp->regs);
|
|
if (lp->sdma_regs)
|
|
iounmap(lp->sdma_regs);
|
|
free_netdev(ndev);
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id temac_of_match[] __devinitdata = {
|
|
{ .compatible = "xlnx,xps-ll-temac-1.01.b", },
|
|
{ .compatible = "xlnx,xps-ll-temac-2.00.a", },
|
|
{ .compatible = "xlnx,xps-ll-temac-2.02.a", },
|
|
{ .compatible = "xlnx,xps-ll-temac-2.03.a", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, temac_of_match);
|
|
|
|
static struct of_platform_driver temac_of_driver = {
|
|
.probe = temac_of_probe,
|
|
.remove = __devexit_p(temac_of_remove),
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "xilinx_temac",
|
|
.of_match_table = temac_of_match,
|
|
},
|
|
};
|
|
|
|
static int __init temac_init(void)
|
|
{
|
|
return of_register_platform_driver(&temac_of_driver);
|
|
}
|
|
module_init(temac_init);
|
|
|
|
static void __exit temac_exit(void)
|
|
{
|
|
of_unregister_platform_driver(&temac_of_driver);
|
|
}
|
|
module_exit(temac_exit);
|
|
|
|
MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
|
|
MODULE_AUTHOR("Yoshio Kashiwagi");
|
|
MODULE_LICENSE("GPL");
|