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https://github.com/edk2-porting/linux-next.git
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c0222ac086
Pull MIPS updates from Ralf Baechle:
"This is an unusually large pull request for MIPS - in parts because
lots of patches missed the 3.18 deadline but primarily because some
folks opened the flood gates.
- Retire the MIPS-specific phys_t with the generic phys_addr_t.
- Improvments for the backtrace code used by oprofile.
- Better backtraces on SMP systems.
- Cleanups for the Octeon platform code.
- Cleanups and fixes for the Loongson platform code.
- Cleanups and fixes to the firmware library.
- Switch ATH79 platform to use the firmware library.
- Grand overhault to the SEAD3 and Malta interrupt code.
- Move the GIC interrupt code to drivers/irqchip
- Lots of GIC cleanups and updates to the GIC code to use modern IRQ
infrastructures and features of the kernel.
- OF documentation updates for the GIC bindings
- Move GIC clocksource driver to drivers/clocksource
- Merge GIC clocksource driver with clockevent driver.
- Further updates to bring the GIC clocksource driver up to date.
- R3000 TLB code cleanups
- Improvments to the Loongson 3 platform code.
- Convert pr_warning to pr_warn.
- Merge a bunch of small lantiq and ralink fixes that have been
staged/lingering inside the openwrt tree for a while.
- Update archhelp for IP22/IP32
- Fix a number of issues for Loongson 1B.
- New clocksource and clockevent driver for Loongson 1B.
- Further work on clk handling for Loongson 1B.
- Platform work for Broadcom BMIPS.
- Error handling cleanups for TurboChannel.
- Fixes and optimization to the microMIPS support.
- Option to disable the FTLB.
- Dump more relevant information on machine check exception
- Change binfmt to allow arch to examine PT_*PROC headers
- Support for new style FPU register model in O32
- VDSO randomization.
- BCM47xx cleanups
- BCM47xx reimplement the way the kernel accesses NVRAM information.
- Random cleanups
- Add support for ATH25 platforms
- Remove pointless locking code in some PCI platforms.
- Some improvments to EVA support
- Minor Alchemy cleanup"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (185 commits)
MIPS: Add MFHC0 and MTHC0 instructions to uasm.
MIPS: Cosmetic cleanups of page table headers.
MIPS: Add CP0 macros for extended EntryLo registers
MIPS: Remove now unused definition of phys_t.
MIPS: Replace use of phys_t with phys_addr_t.
MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT
PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig.
MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdefery
MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO
MIPS: <asm/types.h> fix indentation.
MAINTAINERS: Add entry for BMIPS multiplatform kernel
MIPS: Enable VDSO randomization
MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration
MIPS: Remove declaration of obsolete arch_init_clk_ops()
MIPS: atomic.h: Reformat to fit in 79 columns
MIPS: Apply `.insn' to fixup labels throughout
MIPS: Fix microMIPS LL/SC immediate offsets
MIPS: Kconfig: Only allow 32-bit microMIPS builds
MIPS: signal.c: Fix an invalid cast in ISA mode bit handling
MIPS: mm: Only build one microassembler that is suitable
...
137 lines
2.2 KiB
Plaintext
137 lines
2.2 KiB
Plaintext
config IRQCHIP
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def_bool y
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depends on OF_IRQ
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config ARM_GIC
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config GIC_NON_BANKED
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bool
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config ARM_GIC_V3
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config ARM_NVIC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config ARM_VIC
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config ATMEL_AIC5_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config BCM7120_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config BRCMSTB_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DW_APB_ICTL
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config IMGPDC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config CLPS711X_IRQCHIP
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bool
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depends on ARCH_CLPS711X
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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default y
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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config OMAP_IRQCHIP
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config RENESAS_INTC_IRQPIN
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bool
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select IRQ_DOMAIN
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config RENESAS_IRQC
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bool
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select IRQ_DOMAIN
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on VERSATILE_FPGA_IRQ
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config XTENSA_MX
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bool
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select IRQ_DOMAIN
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config IRQ_CROSSBAR
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bool
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help
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Support for a CROSSBAR ip that precedes the main interrupt controller.
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The primary irqchip invokes the crossbar's callback which inturn allocates
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a free irq and configures the IP. Thus the peripheral interrupts are
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routed to one of the free irqchip interrupt lines.
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config KEYSTONE_IRQ
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tristate "Keystone 2 IRQ controller IP"
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depends on ARCH_KEYSTONE
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help
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Support for Texas Instruments Keystone 2 IRQ controller IP which
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is part of the Keystone 2 IPC mechanism
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config MIPS_GIC
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bool
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select MIPS_CM
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