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88ff663d50
This removes the unused legacy clock code from arch/arm/mach-davinci/. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
208 lines
6.1 KiB
C
208 lines
6.1 KiB
C
/*
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* DaVinci Power & Sleep Controller (PSC) defines
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef __ASM_ARCH_PSC_H
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#define __ASM_ARCH_PSC_H
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/* Power and Sleep Controller (PSC) Domains */
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#define DAVINCI_GPSC_ARMDOMAIN 0
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#define DAVINCI_GPSC_DSPDOMAIN 1
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#define DAVINCI_LPSC_VPSSMSTR 0
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#define DAVINCI_LPSC_VPSSSLV 1
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#define DAVINCI_LPSC_TPCC 2
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#define DAVINCI_LPSC_TPTC0 3
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#define DAVINCI_LPSC_TPTC1 4
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#define DAVINCI_LPSC_EMAC 5
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#define DAVINCI_LPSC_EMAC_WRAPPER 6
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#define DAVINCI_LPSC_USB 9
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#define DAVINCI_LPSC_ATA 10
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#define DAVINCI_LPSC_VLYNQ 11
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#define DAVINCI_LPSC_UHPI 12
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#define DAVINCI_LPSC_DDR_EMIF 13
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#define DAVINCI_LPSC_AEMIF 14
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#define DAVINCI_LPSC_MMC_SD 15
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#define DAVINCI_LPSC_McBSP 17
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#define DAVINCI_LPSC_I2C 18
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#define DAVINCI_LPSC_UART0 19
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#define DAVINCI_LPSC_UART1 20
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#define DAVINCI_LPSC_UART2 21
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#define DAVINCI_LPSC_SPI 22
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#define DAVINCI_LPSC_PWM0 23
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#define DAVINCI_LPSC_PWM1 24
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#define DAVINCI_LPSC_PWM2 25
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#define DAVINCI_LPSC_GPIO 26
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#define DAVINCI_LPSC_TIMER0 27
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#define DAVINCI_LPSC_TIMER1 28
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#define DAVINCI_LPSC_TIMER2 29
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#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
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#define DAVINCI_LPSC_ARM 31
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#define DAVINCI_LPSC_SCR2 32
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#define DAVINCI_LPSC_SCR3 33
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#define DAVINCI_LPSC_SCR4 34
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#define DAVINCI_LPSC_CROSSBAR 35
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#define DAVINCI_LPSC_CFG27 36
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#define DAVINCI_LPSC_CFG3 37
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#define DAVINCI_LPSC_CFG5 38
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#define DAVINCI_LPSC_GEM 39
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#define DAVINCI_LPSC_IMCOP 40
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#define DM355_LPSC_TIMER3 5
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#define DM355_LPSC_SPI1 6
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#define DM355_LPSC_MMC_SD1 7
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#define DM355_LPSC_McBSP1 8
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#define DM355_LPSC_PWM3 10
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#define DM355_LPSC_SPI2 11
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#define DM355_LPSC_RTO 12
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#define DM355_LPSC_VPSS_DAC 41
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/* DM365 */
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#define DM365_LPSC_TIMER3 5
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#define DM365_LPSC_SPI1 6
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#define DM365_LPSC_MMC_SD1 7
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#define DM365_LPSC_McBSP1 8
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#define DM365_LPSC_PWM3 10
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#define DM365_LPSC_SPI2 11
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#define DM365_LPSC_RTO 12
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#define DM365_LPSC_TIMER4 17
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#define DM365_LPSC_SPI0 22
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#define DM365_LPSC_SPI3 38
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#define DM365_LPSC_SPI4 39
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#define DM365_LPSC_EMAC 40
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#define DM365_LPSC_VOICE_CODEC 44
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#define DM365_LPSC_DAC_CLK 46
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#define DM365_LPSC_VPSSMSTR 47
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#define DM365_LPSC_MJCP 50
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/*
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* LPSC Assignments
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*/
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#define DM646X_LPSC_ARM 0
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#define DM646X_LPSC_C64X_CPU 1
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#define DM646X_LPSC_HDVICP0 2
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#define DM646X_LPSC_HDVICP1 3
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#define DM646X_LPSC_TPCC 4
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#define DM646X_LPSC_TPTC0 5
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#define DM646X_LPSC_TPTC1 6
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#define DM646X_LPSC_TPTC2 7
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#define DM646X_LPSC_TPTC3 8
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#define DM646X_LPSC_PCI 13
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#define DM646X_LPSC_EMAC 14
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#define DM646X_LPSC_VDCE 15
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#define DM646X_LPSC_VPSSMSTR 16
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#define DM646X_LPSC_VPSSSLV 17
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#define DM646X_LPSC_TSIF0 18
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#define DM646X_LPSC_TSIF1 19
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#define DM646X_LPSC_DDR_EMIF 20
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#define DM646X_LPSC_AEMIF 21
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#define DM646X_LPSC_McASP0 22
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#define DM646X_LPSC_McASP1 23
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#define DM646X_LPSC_CRGEN0 24
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#define DM646X_LPSC_CRGEN1 25
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#define DM646X_LPSC_UART0 26
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#define DM646X_LPSC_UART1 27
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#define DM646X_LPSC_UART2 28
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#define DM646X_LPSC_PWM0 29
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#define DM646X_LPSC_PWM1 30
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#define DM646X_LPSC_I2C 31
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#define DM646X_LPSC_SPI 32
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#define DM646X_LPSC_GPIO 33
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#define DM646X_LPSC_TIMER0 34
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#define DM646X_LPSC_TIMER1 35
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#define DM646X_LPSC_ARM_INTC 45
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/* PSC0 defines */
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#define DA8XX_LPSC0_TPCC 0
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#define DA8XX_LPSC0_TPTC0 1
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#define DA8XX_LPSC0_TPTC1 2
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#define DA8XX_LPSC0_EMIF25 3
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#define DA8XX_LPSC0_SPI0 4
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#define DA8XX_LPSC0_MMC_SD 5
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#define DA8XX_LPSC0_AINTC 6
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#define DA8XX_LPSC0_ARM_RAM_ROM 7
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#define DA8XX_LPSC0_SECU_MGR 8
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#define DA8XX_LPSC0_UART0 9
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#define DA8XX_LPSC0_SCR0_SS 10
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#define DA8XX_LPSC0_SCR1_SS 11
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#define DA8XX_LPSC0_SCR2_SS 12
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#define DA8XX_LPSC0_PRUSS 13
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#define DA8XX_LPSC0_ARM 14
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#define DA8XX_LPSC0_GEM 15
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/* PSC1 defines */
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#define DA850_LPSC1_TPCC1 0
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#define DA8XX_LPSC1_USB20 1
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#define DA8XX_LPSC1_USB11 2
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#define DA8XX_LPSC1_GPIO 3
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#define DA8XX_LPSC1_UHPI 4
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#define DA8XX_LPSC1_CPGMAC 5
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#define DA8XX_LPSC1_EMIF3C 6
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#define DA8XX_LPSC1_McASP0 7
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#define DA830_LPSC1_McASP1 8
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#define DA850_LPSC1_SATA 8
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#define DA830_LPSC1_McASP2 9
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#define DA850_LPSC1_VPIF 9
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#define DA8XX_LPSC1_SPI1 10
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#define DA8XX_LPSC1_I2C 11
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#define DA8XX_LPSC1_UART1 12
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#define DA8XX_LPSC1_UART2 13
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#define DA850_LPSC1_McBSP0 14
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#define DA850_LPSC1_McBSP1 15
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#define DA8XX_LPSC1_LCDC 16
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#define DA8XX_LPSC1_PWM 17
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#define DA850_LPSC1_MMC_SD1 18
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#define DA8XX_LPSC1_ECAP 20
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#define DA830_LPSC1_EQEP 21
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#define DA850_LPSC1_TPTC2 21
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#define DA8XX_LPSC1_SCR_P0_SS 24
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#define DA8XX_LPSC1_SCR_P1_SS 25
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#define DA8XX_LPSC1_CR_P3_SS 26
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#define DA8XX_LPSC1_L3_CBA_RAM 31
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/* PSC register offsets */
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#define EPCPR 0x070
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#define PTCMD 0x120
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#define PTSTAT 0x128
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#define PDSTAT 0x200
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#define PDCTL 0x300
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#define MDSTAT 0x800
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#define MDCTL 0xA00
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/* PSC module states */
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#define PSC_STATE_SWRSTDISABLE 0
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#define PSC_STATE_SYNCRST 1
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#define PSC_STATE_DISABLE 2
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#define PSC_STATE_ENABLE 3
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#define MDSTAT_STATE_MASK 0x3f
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#define PDSTAT_STATE_MASK 0x1f
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#define MDCTL_LRST BIT(8)
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#define MDCTL_FORCE BIT(31)
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#define PDCTL_NEXT BIT(0)
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#define PDCTL_EPCGOOD BIT(8)
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#endif /* __ASM_ARCH_PSC_H */
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