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7416d44113
The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time, it equires a special enable method to get it started. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
97 lines
2.4 KiB
C
97 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* R9A06G032 Second CA7 enabler.
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*
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* Copyright (C) 2018 Renesas Electronics Europe Limited
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*
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* Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
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* Derived from actions,s500-smp
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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/*
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* The second CPU is parked in ROM at boot time. It requires waking it after
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* writing an address into the BOOTADDR register of sysctrl.
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*
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* So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
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*
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* *However* the BOOTADDR register is not available when the kernel
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* starts in NONSEC mode.
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*
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* So for NONSEC mode, the bootloader re-parks the second CPU into a pen
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* in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
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* which is not restricted.
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*/
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static void __iomem *cpu_bootaddr;
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static DEFINE_SPINLOCK(cpu_lock);
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static int
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r9a06g032_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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if (!cpu_bootaddr)
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return -ENODEV;
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spin_lock(&cpu_lock);
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writel(__pa_symbol(secondary_startup), cpu_bootaddr);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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spin_unlock(&cpu_lock);
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return 0;
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}
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static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *dn;
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int ret = -EINVAL, dns;
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u32 bootaddr;
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dn = of_get_cpu_node(1, NULL);
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if (!dn) {
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pr_err("CPU#1: missing device tree node\n");
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return;
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}
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/*
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* Determine the address from which the CPU is polling.
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* The bootloader *does* change this property.
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* Note: The property can be either 64 or 32 bits, so handle both cases
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*/
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if (of_find_property(dn, "cpu-release-addr", &dns)) {
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if (dns == sizeof(u64)) {
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u64 temp;
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ret = of_property_read_u64(dn,
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"cpu-release-addr", &temp);
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bootaddr = temp;
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} else {
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ret = of_property_read_u32(dn,
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"cpu-release-addr",
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&bootaddr);
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}
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}
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of_node_put(dn);
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if (ret) {
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pr_err("CPU#1: invalid cpu-release-addr property\n");
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return;
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}
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pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr);
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cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr));
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}
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static const struct smp_operations r9a06g032_smp_ops __initconst = {
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.smp_prepare_cpus = r9a06g032_smp_prepare_cpus,
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.smp_boot_secondary = r9a06g032_smp_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(r9a06g032_smp,
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"renesas,r9a06g032-smp", &r9a06g032_smp_ops);
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