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be10afcd22
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
37 lines
860 B
Plaintext
37 lines
860 B
Plaintext
Binding for a ST pre-divider clock driver.
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This binding uses the common clock binding[1].
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Base address is located to the parent node. See clock binding[2]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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Required properties:
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- compatible : shall be:
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"st,clkgena-prediv-c65", "st,clkgena-prediv"
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"st,clkgena-prediv-c32", "st,clkgena-prediv"
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- #clock-cells : From common clock binding; shall be set to 0.
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- clocks : From common clock binding
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- clock-output-names : From common clock binding.
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Example:
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clockgenA@fd345000 {
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reg = <0xfd345000 0xb50>;
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CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c32",
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"st,clkgena-prediv";
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clocks = <&CLK_SYSIN>;
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clock-output-names = "CLK_M_A2_OSC_PREDIV";
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};
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};
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